powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support
Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>utp
Scott Wood
parent
c97cd1ba48
commit
94a45bb197
9
README
9
README
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@ -2653,6 +2653,10 @@ FIT uImage format:
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CONFIG_SPL_TEXT_BASE
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TEXT_BASE for linking the SPL binary.
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CONFIG_SPL_RELOC_TEXT_BASE
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Address to relocate to. If unspecified, this is equal to
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CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
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CONFIG_SPL_BSS_START_ADDR
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Link address for the BSS within the SPL binary.
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@ -2662,6 +2666,11 @@ FIT uImage format:
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CONFIG_SPL_STACK
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Adress of the start of the stack SPL will use
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CONFIG_SPL_RELOC_STACK
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Adress of the start of the stack SPL will use after
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relocation. If unspecified, this is equal to
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CONFIG_SPL_STACK.
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CONFIG_SYS_SPL_MALLOC_START
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Starting address of the malloc pool used in SPL.
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@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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COBJS-y += spl_minimal.o tlb.o law.o
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else
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -177,7 +177,7 @@ void board_gpio_init(void)
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*/
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setbits_be32(&pgpio->gpdir, 0x02130000);
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#ifndef CONFIG_SYS_RAMBOOT
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#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
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/* init DDR3 reset signal */
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setbits_be32(&pgpio->gpdir, 0x00200000);
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setbits_be32(&pgpio->gpodr, 0x00200000);
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@ -0,0 +1,131 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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void sdram_init(void)
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{
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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#endif
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
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/* Set, but do not enable the memory */
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
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asm volatile("sync;isync");
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udelay(500);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#ifndef CONFIG_QE
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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#endif
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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#ifndef CONFIG_QE
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/* init DDR3 reset signal */
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__raw_writel(0x02000000, &pgpio->gpdir);
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__raw_writel(0x00200000, &pgpio->gpodr);
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__raw_writel(0x00000000, &pgpio->gpdat);
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udelay(1000);
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__raw_writel(0x00200000, &pgpio->gpdat);
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udelay(1000);
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__raw_writel(0x00000000, &pgpio->gpdir);
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#endif
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/* Initialize the DDR3 */
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sdram_init();
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_NAND_SPL
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#ifndef CONFIG_SPL_BUILD
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/* W**G* - Flash/promjet, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_64K, 1),
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#endif
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#endif /* not SPL */
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#ifdef CONFIG_SYS_NAND_BASE
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/* *I*G - NAND */
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@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 7, BOOKE_PAGESZ_1M, 1),
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#endif
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#ifdef CONFIG_SYS_RAMBOOT
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
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/* *I*G - eSDHC/eSPI/NAND boot */
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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@ -108,7 +108,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 9, BOOKE_PAGESZ_1G, 1),
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#endif
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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