zymqmp: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>utp
Alexander Graf
Tom Rini
parent
d473f0c621
commit
96519f31cb
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@ -8,6 +8,7 @@
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#define ZYNQ_SILICON_VER_MASK 0xF000
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@ -15,6 +16,53 @@
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region zynqmp_mem_map[] = {
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{
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.base = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.base = 0x80000000UL,
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.size = 0x70000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.base = 0xf8000000UL,
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.size = 0x07e00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.base = 0xffe00000UL,
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.size = 0x00200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.base = 0x400000000UL,
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.size = 0x200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.base = 0x600000000UL,
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.size = 0x800000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.base = 0xe00000000UL,
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.size = 0xf200000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = zynqmp_mem_map;
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static unsigned int zynqmp_get_silicon_version_secure(void)
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{
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u32 ver;
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@ -44,172 +92,3 @@ unsigned int zynqmp_get_silicon_version(void)
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return ZYNQMP_CSU_VERSION_SILICON;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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#include <asm/armv8/mmu.h>
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#define SECTION_SHIFT_L1 30UL
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#define SECTION_SHIFT_L2 21UL
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#define BLOCK_SIZE_L0 0x8000000000UL
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#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
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#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
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#define TCR_TG1_4K (1 << 31)
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#define TCR_EPD1_DISABLE (1 << 23)
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#define ZYNQMO_VA_BITS 40
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#define ZYNQMP_TCR TCR_TG1_4K | \
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TCR_EPD1_DISABLE | \
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TCR_SHARED_OUTER | \
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TCR_SHARED_INNER | \
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TCR_IRGN_WBWA | \
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TCR_ORGN_WBWA | \
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TCR_T0SZ(ZYNQMO_VA_BITS)
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#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \
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PMD_ATTRINDX(MT_NORMAL) | \
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PMD_TYPE_SECT
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#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \
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PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
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PMD_TYPE_SECT
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/* 4K size is required to place 512 entries in each level */
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#define TLB_TABLE_SIZE 0x1000
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struct attr_tbl {
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u32 num;
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u64 attr;
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};
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static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
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{8, DEVICE_ATTR},
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{32, MEMORY_ATTR},
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{456, DEVICE_ATTR}
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};
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static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
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{0x40, 0x0},
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{0x3F, DEVICE_ATTR},
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{0x1, MEMORY_ATTR}
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};
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/*
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* This mmu table looks as below
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* Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
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* and other Level1 Table1.
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* Level1 Table0 contains entries for each 1GB from 0 to 511GB.
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* Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
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* Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
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* entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
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*/
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static void zynqmp_mmu_setup(void)
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{
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int el;
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u32 index_attr;
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u64 i, section_l1t0, section_l1t1;
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u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
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u64 *level0_table = (u64 *)gd->arch.tlb_addr;
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u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
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u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
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u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
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u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
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u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
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u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
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level0_table[0] =
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(u64)level1_table_0 | PMD_TYPE_TABLE;
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level0_table[1] =
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(u64)level1_table_1 | PMD_TYPE_TABLE;
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/*
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* set level 1 table 0, covering 0 to 512GB
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* set level 1 table 1, covering 512GB to 1TB
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*/
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section_l1t0 = 0;
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section_l1t1 = BLOCK_SIZE_L0;
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index_attr = 0;
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for (i = 0; i < 512; i++) {
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level1_table_0[i] = section_l1t0;
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level1_table_0[i] |= attr_tbll1t0[index_attr].attr;
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attr_tbll1t0[index_attr].num--;
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if (attr_tbll1t0[index_attr].num == 0)
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index_attr++;
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level1_table_1[i] = section_l1t1;
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level1_table_1[i] |= DEVICE_ATTR;
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section_l1t0 += BLOCK_SIZE_L1;
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section_l1t1 += BLOCK_SIZE_L1;
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}
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level1_table_0[0] =
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(u64)level2_table_0 | PMD_TYPE_TABLE;
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level1_table_0[1] =
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(u64)level2_table_1 | PMD_TYPE_TABLE;
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level1_table_0[2] =
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(u64)level2_table_2 | PMD_TYPE_TABLE;
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level1_table_0[3] =
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(u64)level2_table_3 | PMD_TYPE_TABLE;
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section_l2t0 = 0;
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section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
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section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
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section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
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index_attr = 0;
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for (i = 0; i < 512; i++) {
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level2_table_0[i] = section_l2t0 | MEMORY_ATTR;
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level2_table_1[i] = section_l2t1 | MEMORY_ATTR;
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level2_table_2[i] = section_l2t2 | DEVICE_ATTR;
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level2_table_3[i] = section_l2t3 |
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attr_tbll2t3[index_attr].attr;
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attr_tbll2t3[index_attr].num--;
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if (attr_tbll2t3[index_attr].num == 0)
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index_attr++;
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section_l2t0 += BLOCK_SIZE_L2;
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section_l2t1 += BLOCK_SIZE_L2;
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section_l2t2 += BLOCK_SIZE_L2;
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section_l2t3 += BLOCK_SIZE_L2;
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}
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/* flush new MMU table */
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flush_dcache_range(gd->arch.tlb_addr,
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gd->arch.tlb_addr + gd->arch.tlb_size);
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/* point TTBR to the new table */
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el = current_el();
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set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
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ZYNQMP_TCR, MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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int arch_cpu_init(void)
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{
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icache_enable();
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__asm_invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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return 0;
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}
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/*
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* This function is called from lib/board.c.
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* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
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* There is no need to disable d-cache for this operation.
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*/
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void enable_caches(void)
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{
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/* The data cache is not active unless the mmu is enabled */
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if (!(get_sctlr() & CR_M)) {
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invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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zynqmp_mmu_setup();
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}
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puts("Enabling Caches...\n");
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set_sctlr(get_sctlr() | CR_C);
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}
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u64 *arch_get_page_table(void)
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{
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return (u64 *)(gd->arch.tlb_addr + 0x3000);
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}
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#endif
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@ -29,6 +29,8 @@
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_FULL_VA
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/* Have release address at the end of 256MB for now */
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#define CPU_RELEASE_ADDR 0xFFFFFF0
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