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i2c: tegra: write clean data to TX FIFO 

The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.

Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
utp
Stephen Warren 2014-06-25 10:57:28 -06:00 committed by Heiko Schocher
parent 68049a082b
commit 981b14f01a
1 changed files with 7 additions and 5 deletions
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12
drivers/i2c/tegra_i2c.c
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@ -224,14 +224,16 @@ static int send_recv_packets(struct i2c_bus *i2c_bus,
if (is_write) {
/* deal with word alignment */
if ((unsigned)dptr & 3) {
if ((words == 1) && last_bytes) {
local = 0;
memcpy(&local, dptr, last_bytes);
} else if ((unsigned)dptr & 3) {
memcpy(&local, dptr, sizeof(u32));
writel(local, &control->tx_fifo);
debug("pkt data sent (0x%x)\n", local);
} else {
writel(*wptr, &control->tx_fifo);
debug("pkt data sent (0x%x)\n", *wptr);
local = *wptr;
}
writel(local, &control->tx_fifo);
debug("pkt data sent (0x%x)\n", local);
if (!wait_for_tx_fifo_empty(control)) {
error = -1;
goto exit;