net: tsec: fsl_mdio: Fix several cosmetic issues
Clean up the tsec and fsl_mdio driver codes a little bit, by: - Fix misuse of tab and space here and there - Use correct multi-line comment format - Replace license identifier to GPL-2.0+ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>utp
Bin Meng
Joe Hershberger
parent
9ccb309651
commit
9872b736f9
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@ -5,6 +5,7 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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@ -32,8 +33,7 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
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int value;
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int timeout = 1000000;
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/* Put the address of the phy, and the register
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* number into MIIMADD */
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/* Put the address of the phy, and the register number into MIIMADD */
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out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
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/* Clear the command register, and wait */
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@ -1,14 +1,11 @@
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/*
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* Freescale Three Speed Ethernet Controller driver
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* author Andy Fleming
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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@ -84,8 +81,10 @@ static struct tsec_info_struct tsec_info[] = {
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/* Configure the TBI for SGMII operation */
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static void tsec_configure_serdes(struct tsec_private *priv)
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{
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/* Access TBI PHY registers at given TSEC register offset as opposed
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* to the register offset used for external PHY accesses */
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/*
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* Access TBI PHY registers at given TSEC register offset as opposed
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* to the register offset used for external PHY accesses
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*/
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_ANA, TBIANA_SETTINGS);
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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@ -100,7 +99,8 @@ static void tsec_configure_serdes(struct tsec_private *priv)
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/* Set the appropriate hash bit for the given addr */
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/* The algorithm works like so:
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/*
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* The algorithm works like so:
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* 1) Take the Destination Address (ie the multicast address), and
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* do a CRC on it (little endian), and reverse the bits of the
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* result.
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@ -111,9 +111,9 @@ static void tsec_configure_serdes(struct tsec_private *priv)
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* hash index which gaddr register to use, and the 5 other bits
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* indicate which bit (assuming an IBM numbering scheme, which
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* for PowerPC (tm) is usually the case) in the register holds
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* the entry. */
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static int
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tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
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* the entry.
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*/
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static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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@ -135,7 +135,8 @@ tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
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}
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#endif /* Multicast TFTP ? */
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/* Initialized required registers to appropriate values, zeroing
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/*
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* Initialized required registers to appropriate values, zeroing
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* those we don't care about (unless zero is bad, in which case,
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* choose a more appropriate value)
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*/
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@ -181,7 +182,8 @@ static void init_registers(struct tsec __iomem *regs)
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}
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/* Configure maccfg2 based on negotiated speed and duplex
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/*
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* Configure maccfg2 based on negotiated speed and duplex
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* reported by PHY handling code
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*/
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static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
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@ -212,7 +214,8 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
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case 10:
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maccfg2 |= MACCFG2_MII;
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/* Set R100 bit in all modes although
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/*
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* Set R100 bit in all modes although
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* it is only used in RGMII mode
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*/
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if (phydev->speed == 100)
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@ -315,7 +318,8 @@ void redundant_init(struct eth_device *dev)
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}
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#endif
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/* Set up the buffers and their descriptors, and bring up the
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/*
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* Set up the buffers and their descriptors, and bring up the
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* interface
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*/
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static void startup_tsec(struct eth_device *dev)
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@ -369,9 +373,10 @@ static void startup_tsec(struct eth_device *dev)
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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}
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/* This returns the status bits of the device. The return value
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/*
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* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* do the same. Presumably, this would be zero if there were no
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* errors
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*/
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static int tsec_send(struct eth_device *dev, void *packet, int length)
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@ -446,7 +451,6 @@ static int tsec_recv(struct eth_device *dev)
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}
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return -1;
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}
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/* Stop the interface */
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@ -468,10 +472,11 @@ static void tsec_halt(struct eth_device *dev)
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phy_shutdown(priv->phydev);
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}
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/* Initializes data structures and registers for the controller,
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* and brings the interface up. Returns the link status, meaning
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/*
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* Initializes data structures and registers for the controller,
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* and brings the interface up. Returns the link status, meaning
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* that it returns success if the link is up, failure otherwise.
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* This allows u-boot to find the first active controller.
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* This allows U-Boot to find the first active controller.
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*/
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static int tsec_init(struct eth_device *dev, bd_t * bd)
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{
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@ -489,7 +494,8 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
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/* Init ECNTRL */
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out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
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/* Copy the station address into the address registers.
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/*
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* Copy the station address into the address registers.
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* For a station address of 0x12345678ABCD in transmission
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* order (BE), MACnADDR1 is set to 0xCDAB7856 and
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* MACnADDR2 is set to 0x34120000.
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@ -551,8 +557,8 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv)
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* be set by the platform code.
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*/
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if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
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(interface == PHY_INTERFACE_MODE_RGMII_RXID))
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(interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
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(interface == PHY_INTERFACE_MODE_RGMII_RXID))
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return interface;
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return PHY_INTERFACE_MODE_RGMII;
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@ -565,8 +571,8 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv)
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return PHY_INTERFACE_MODE_MII;
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}
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/* Discover which PHY is attached to the device, and configure it
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/*
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* Discover which PHY is attached to the device, and configure it
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* properly. If the PHY is not recognized, then return 0
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* (failure). Otherwise, return 1
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*/
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@ -605,7 +611,8 @@ static int init_phy(struct eth_device *dev)
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return 1;
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}
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/* Initialize device structure. Returns success if PHY
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/*
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* Initialize device structure. Returns success if PHY
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* initialization succeeded (i.e. if it recognizes the PHY)
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*/
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static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
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@ -645,7 +652,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
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dev->mcast = tsec_mcast_addr;
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#endif
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/* Tell u-boot to get the addr from the env */
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/* Tell U-Boot to get the addr from the env */
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for (i = 0; i < 6; i++)
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dev->enetaddr[i] = 0;
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@ -5,6 +5,7 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_PHY_H__
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#define __FSL_PHY_H__
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@ -27,9 +28,9 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
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#define PHY_EXT_PAGE_ACCESS 0x1f
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/* MII Management Configuration Register */
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#define MIIMCFG_RESET_MGMT 0x80000000
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#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
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#define MIIMCFG_INIT_VALUE 0x00000003
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#define MIIMCFG_RESET_MGMT 0x80000000
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#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
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#define MIIMCFG_INIT_VALUE 0x00000003
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/* MII Management Command Register */
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#define MIIMCOM_READ_CYCLE 0x00000001
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@ -3,15 +3,12 @@
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*
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* Driver for the Motorola Triple Speed Ethernet Controller
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* maintained by Xianghua Xiao (x.xiao@motorola.com)
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* author Andy Fleming
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TSEC_H
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@ -67,11 +64,11 @@
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x.mii_devname = DEFAULT_MII_NAME;\
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}
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#define MAC_ADDR_LEN 6
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#define MAC_ADDR_LEN 6
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/* #define TSEC_TIMEOUT 1000000 */
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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/* TBI register addresses */
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#define TBI_CR 0x00
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@ -83,8 +80,8 @@
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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@ -93,13 +90,12 @@
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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/* MAC register bits */
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#define MACCFG1_SOFT_RESET 0x80000000
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#define MACCFG1_RESET_RX_MC 0x00080000
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#define MACCFG1_RESET_TX_MC 0x00040000
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#define MACCFG1_RESET_RX_FUN 0x00020000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_LOOPBACK 0x00000100
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#define MACCFG1_RX_FLOW 0x00000020
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#define MACCFG1_TX_FLOW 0x00000010
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@ -122,7 +118,7 @@
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#define ECNTRL_SGMII_MODE 0x00000002
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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# define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
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@ -137,7 +133,6 @@
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#define TSTAT_CLEAR_THALT 0x80000000
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#define RSTAT_CLEAR_RHALT 0x00800000
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#define IEVENT_INIT_CLEAR 0xffffffff
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#define IEVENT_BABR 0x80000000
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#define IEVENT_RXC 0x40000000
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@ -164,11 +159,9 @@
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#define IMASK_TXFEN 0x00100000
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#define IMASK_RXFEN0 0x00000080
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/* Default Attribute fields */
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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/* TxBD status field bits */
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#define TXBD_READY 0x8000
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@ -181,7 +174,7 @@
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#define TXBD_HUGEFRAME 0x0080
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#define TXBD_LATECOLLISION 0x0080
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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#define TXBD_STATS 0x03ff
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@ -204,15 +197,15 @@
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#define RXBD_STATS 0x003f
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struct txbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer length */
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uint32_t bufptr; /* Buffer Pointer */
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct rxbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer Length */
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uint32_t bufptr; /* Buffer Pointer */
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer Length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct tsec_rmon_mib {
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@ -336,15 +329,15 @@ struct tsec {
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u32 rbdlen; /* RxBD Data Length */
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u32 res310[4];
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u32 res320;
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 res328[6];
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 res344[16];
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u32 rbptr; /* RxBD Pointer */
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u32 rbptr; /* RxBD Pointer */
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u32 res388[30];
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/* (0x2_n400) */
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u32 res400;
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u32 rbase; /* RxBD Base Address */
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u32 rbase; /* RxBD Base Address */
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u32 res408[62];
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/* MAC Registers (0x2_n500) */
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@ -388,7 +381,7 @@ struct tsec {
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u32 resc00[256];
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};
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#define TSEC_GIGABIT (1 << 0)
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#define TSEC_GIGABIT (1 << 0)
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/* These flags currently only have meaning if we're using the eTSEC */
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#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
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