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Merge branch 'master' into u-boot-5329-early

utp
John Rigby 2007-07-10 14:58:41 -06:00
parent 0dca874db6 4ef218f6fd
commit 98c80b462f
192 changed files with 9616 additions and 1419 deletions
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567
CHANGELOG
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@ -1,3 +1,359 @@
commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Jul 6 02:50:19 2007 +0200
Code cleanup and default config update for STC GP3 SSA board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit b44896215a09c60fa40cae906f7ed207bbc2c492
Author: Sergei Poselenov <sposelenov@emcraft.com>
Date: Thu Jul 5 08:17:37 2007 +0200
Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
commit f780b83316d9af1f61d71cc88b1917b387b9b995
Author: Niklaus Giger <niklausgiger@gmx.ch>
Date: Wed Jun 27 18:11:38 2007 +0200
resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4
Author: Stefan Roese <sr@denx.de>
Date: Wed Jul 4 10:06:30 2007 +0200
ppc4xx: Update lwmon5 board
- Add optional ECC generation routine to preserve existing
RAM values. This is needed for the Linux log-buffer support
- Add optional DDR2 setup with CL=4
- GPIO50 not used anymore
- Lime register setup added
Signed-off-by: Stefan Roese <sr@denx.de>
commit 1f2a05898658900dc5717761e27abf2052e67e13
Author: Mushtaq Khan <mushtaqk_921@yahoo.co.in>
Date: Sat Jun 30 18:50:48 2007 +0200
Fix S-ATA support.
Signed-off-by: mushtaq khan <mushtaqk_921@yahoo.co.in>
commit a5d71e290f3673269be8eefb4ec44f53412f9461
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Mon Jun 25 19:11:37 2007 +0200
[PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG
Signed-off-by: Heiko Schocher <hs@denx.de>
commit a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b
Author: Niklaus Giger <niklaus.giger@nestal.com>
Date: Mon Jun 25 17:03:13 2007 +0200
ppc4xx: PPC440EPx Emit DDR0 registers on machine check interrupt
This patch prints the DDR status registers upon machine check
interrupt on the 440EPx/GRx. This can be useful especially when
ECC support is enabled.
I added some small changes to the original patch from Niklaus to
make it compile clean.
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 807018fb7faceb429ce0cb47baa2073746b33a4e
Author: Niklaus Giger <niklaus.giger@nestal.com>
Date: Mon Jun 25 16:50:55 2007 +0200
ppc4xx: Fix O=buildir builds
This patch fixes the problem to assemble cpu/ppc4xx/start.S
experienced last week where building failed having specified
O=../build.sequoia.
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
commit 466fff1a7bb5fe764a06450626f6098219f446b8
Author: Stefan Roese <sr@denx.de>
Date: Mon Jun 25 15:57:39 2007 +0200
ppc4xx: Add pci_pre_init() for 405 boards
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6f35c53166213c24a5a0e2390ed861136ff73870
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Sun Jun 24 17:41:21 2007 +0200
ppc4xx: Maintenance patch for esd's CPCI405 derivats
-add pci_pre_init() for pci interrupt fixup code
-disable phy sleep mode via reset_phy() function
-use correct io accessors
-cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit 5a1c9ff0c44305b57cb4d8f9369bba90bcf0e1f8
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Sun Jun 24 17:23:41 2007 +0200
ppc4xx: Add pci_pre_init() for 405 boards
This patch adds support for calling a plattform dependant
pci_pre_init() function for 405 boards. This can be used to
move the current pci_405gp_fixup_irq() function into the
board code.
This patch also makes the CFG_PCI_PRE_INIT define obsolete.
A default function with 'weak' attribute is used when
a board specific pci_pre_init() is not implemented.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit 1636d1c8529c006d106287cfbc20cd0a246fe1cb
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Jun 22 23:59:00 2007 +0200
Coding stylke cleanup; rebuild CHANGELOG
commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Apr 18 14:55:19 2007 +0400
Adapt log buffer code to support Linux 2.6
A new environment variable, "logversion", selects the log buffer
behaviour. If it is not set or set to a value other than 2, then the
old, Linux 2.4.4, behaviour is selected.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit a11e06965ec91270c51853407ff1261d3c740386
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Mar 28 19:06:19 2007 +0400
Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit 566a494f592ae3b3c0785d90d4e1ba45574880c4
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jun 22 19:11:54 2007 +0200
[PCS440EP] upgrade the PCS440EP board:
- Show on the Status LEDs, some States of the board.
- Get the MAC addresses from the EEProm
- use PREBOOT
- use the CF on the board.
- check the U-Boot image in the Flash with a SHA1
checksum.
- use dynamic TLB entries generation for the SDRAM
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 3a1f5c81b0b9557817a789bece839905581c2205
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 22 16:58:40 2007 +0200
ppc4xx: Fix problem with extended program_tlb() funtion
The recently extended program_tlb() function had a problem when
multiple TLB's had to be setup (for example with 512MB of SDRAM). The
virtual address was not incremented. This patch fixes this issue
and is tested on Katmai with 512MB SDRAM.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jun 22 14:58:04 2007 +0200
[ppc] Fix build breakage for all non-4xx PowerPC variants.
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 20 18:14:24 2007 +0200
Coding style cleanup. Refresh CHANGELOG.
commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 17:22:44 2007 +0200
ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board
This patch adds a board command to configure the I2C bootstrap EEPROM
values. Right now 533 and 667MHz are supported for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 533 nor ;to configure the board for 533MHz NOR booting
=> bootstrap 667 nand ;to configure the board for 667MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
commit df8a24cdd30151505cf57bbee5289e91bf53bd1b
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 16:42:31 2007 +0200
[ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 86ba99e34194394052d24c04dc40d1263d29a26f
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 16:40:58 2007 +0200
[ppc4xx] Change board/amcc/acadia/cpr.c to pll.c
Signed-off-by: Stefan Roese <sr@denx.de>
commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 11:33:41 2007 +0200
[ppc4xx] Change lwmon5 port to work with recent 440 exception rework
Now CONFIG_440 has to be defined in all PPC440 board config files.
Signed-off-by: Stefan Roese <sr@denx.de>
commit efa35cf12d914d4caba942acd5a6c45f217de302
Author: Grzegorz Bernacki <gjb@semihalf.com>
Date: Fri Jun 15 11:19:28 2007 +0200
ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
for 440-specific machine instructions like 'rfmci' etc.
- Exception vectors moved to the proper location (_start moved away from
the critical exception handler space, which it occupied)
- CriticalInput now serviced (with default handler)
- MachineCheck properly serviced (added a dedicated handler and return
subroutine)
- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
unhandled and those not relevant for 4xx were eliminated)
- Eliminated Linux leftovers, removed dead code
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 08:18:01 2007 +0200
[ppc4xx] Add initial lwmon5 board support
This patch adds initial support for the Liebherr lwmon5 board euqipped
with an AMCC 440EPx PowerPC.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 85f737376d5ff3d5f0d45a8b657686326d175307
Author: Stefan Roese <sr@denx.de>
Date: Fri Jun 15 07:39:43 2007 +0200
[ppc4xx] Extend 44x GPIO setup with default output state
The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
is extended with the default GPIO output state (level).
Signed-off-by: Stefan Roese <sr@denx.de>
commit dbca208518e5e7f01a6420588d1cd6e60db74c2b
Author: Stefan Roese <sr@denx.de>
Date: Thu Jun 14 11:14:32 2007 +0200
[ppc4xx] Extend program_tlb() with virtual & physical addresses
Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88
Author: Detlev Zundel <dzu@denx.de>
Date: Wed May 23 19:02:41 2007 +0200
Change 'repeatable' attribute of some commands to sensible values.
Most prominently this changes 'erase' to be non-repeatable.
Signed-off-by: Detlev Zundel <dzu@denx.de>
commit 5afb202093f6a001797db92cf695b93a70ea9ab4
Author: Detlev Zundel <dzu@denx.de>
Date: Wed May 23 18:47:48 2007 +0200
Fix 'run' not to continue after interrupted command
Signed-off-by: Detlev Zundel <dzu@denx.de>
commit 8f8416fada9faf94b9a92f21fe6000643cb521d5
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Fri Jun 8 14:52:22 2007 +0200
TQM5200: Add Flat Device Tree support, update default env. accordingly.
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
commit 9045f33c023f698660a2e45d1b2194c0711abebc
Author: Wolfgang Denk <wd@denx.de>
Date: Fri Jun 8 10:24:58 2007 +0200
Fix config problems on SC3 board; make ide_reset_timeout work.
commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b
Author: Benoît Monin <bmonin@adeneo.eu>
Date: Fri Jun 8 09:55:24 2007 +0200
[PATCH] fix gpio setting when using CFG_440_GPIO_TABLE
Set the correct value in GPIOx_TCR when configuring the gpio
with CFG_440_GPIO_TABLE.
Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 6 16:26:56 2007 +0200
Coding Style cleanup; generate new CHANGELOG file.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c440bfe6d6d92d66478a7e84402b31f48413617b
Author: Stefan Roese <sr@denx.de>
Date: Wed Jun 6 11:42:13 2007 +0200
@ -328,6 +684,14 @@ Date: Thu May 24 08:22:09 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
commit 822d55365bb557e084d0e33625a6dedcc866110b
Author: Jon Loeliger <jdl@freescale.com>
Date: Wed May 23 14:09:46 2007 -0500
Add LIST_86xx MAKEALL target for PowerPC builds.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
commit 9f0077abd69f7a7c756a915b961037302be3e6f2
Author: Stefan Roese <sr@denx.de>
Date: Tue May 22 12:48:09 2007 +0200
@ -376,6 +740,17 @@ Date: Fri May 18 14:33:11 2007 +0100
Makefile permissions
commit 255a3577c848706441daee0174543efe205a77f8
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed May 16 16:52:19 2007 -0500
Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit 70124c2602ae2d4c5d3dba05b482d91548242de8
Author: Stefano Babic <sbabic@denx.de>
Date: Wed May 16 14:49:12 2007 +0200
@ -417,6 +792,109 @@ Date: Wed May 16 00:13:33 2007 +0200
Coding Style Cleanup, new CHANGELOG
commit 3162eb836903c8b247fdc7470dd39bfa6996f495
Author: Wolfgang Denk <wd@denx.de>
Date: Tue May 15 23:38:05 2007 +0200
Minor coding style cleanup.
commit 66d9dbec1cc27d6398ee6cf84639dbe14971251e
Author: mushtaq khan <mushtaq_k@procsys.com>
Date: Fri Apr 20 14:23:02 2007 +0530
Add driver for S-ATA-controller on Intel processors with South
Bridge, ICH-5, ICH-6 and ICH-7.
Implementation:
1. Code is divided in to two files. All functions, which are
controller specific are kept in "drivers/ata_piix.c" file and
functions, which are not controller specific, are kept in
"common/cmd_sata.c" file.
2. Reading and Writing from the S-ATA drive is done using PIO method.
3. Driver can be configured for 48-bit addressing by defining macro
CONFIG_LBA48, if this macro is not defined driver uses the 28-bit
addressing.
4. S-ATA read function is hooked to the File system, commands like
ext2ls and ext2load file can be used. This has been tested.
5. U-Boot command "SATA_init" is added, which initializes the S-ATA
controller and identifies the S-ATA drives connected to it.
6. U-Boot command "sata" is added, which is used to read/write, print
partition table and get info about the drives present. This I have
implemented in same way as "ide" command is implemented in U-Boot.
7. This driver is for S-ATA in native mode.
8. This driver does not support the Native command queuing and
Hot-plugging.
Signed-off-by: Mushtaq Khan <mushtaq_k@procsys.com>
commit 644e6fb4eb8be90ea04ba34b643a8bf019d680e0
Author: mushtaq khan <mushtaq_k@procsys.com>
Date: Mon Apr 30 15:57:22 2007 +0530
Fixes bug clearing the bss section for i386
Hi,
There is a bug in the code of clearing the bss section for processor
i386.(File: cpu/i386/start.S)
In the code, bss_start addr (starting addr of bss section) is put into
the register %eax, but the code which clears the bss section refers to
the addr pointed by %edi.
This patch fixes this bug by putting bss_start into %edi register.
Signed-off-by: Mushtaq Khan <mushtaq_k@procsys.com>
commit c3243cf7b490057277d61acffe4ad0946f9eb4a4
Author: Joe Hamman <joe.hamman@embeddedspecialties.com>
Date: Mon Apr 30 16:47:28 2007 -0500
Add support for BCM5464 Quad Phy
Added support for Broadcom's BCM5464 Quad Phy
Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com>
commit 1b305bdc754c8468e1d5d858f5dcf8a7a0a4bb7a
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
Date: Wed May 9 08:10:57 2007 +0800
Search the exception table with linear algorithm
Search the exception table with linear algorithm instead of
bisecting algorithm.
Because the exception table might be unsorted.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
commit 5dfaa50eb819686bfba1927e8c5b8a70a4d65fd3
Author: Aubrey.Li <aubrey.adi@gmail.com>
Date: Mon May 14 11:47:35 2007 +0800
Fix compilation issues on MACOSX
Singed-off-by: Marc Hoffman <Marc.Hoffman@analog.com>
Signed-off-by: Aubrey Li <aubrey.adi@gmail.com>
commit 56fd7162985c412317bbf763a225fba23c64fd31
Author: Stephen Williams <steve@icarus.com>
Date: Tue May 15 07:55:42 2007 -0700
Fix for compile of JSE target
The attached patch fixes the compile of the JSE board in the
denx git as of 14 may 2007. It is an extremely simple patch,
it just adds the missing define of CFG_SYSTEMACE_WIDTH.
Fix to compile JSE against 20070514 git of u-boot
commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
Author: Stefan Roese <sr@denx.de>
Date: Fri May 11 12:01:49 2007 +0200
@ -756,6 +1234,20 @@ Date: Sat May 5 08:29:01 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
commit 2f550ab976405300f5b07bf2890800840d0aa05f
Author: Timur Tabi <timur@freescale.com>
Date: Sat May 5 08:12:30 2007 +0200
5xxx: write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both. To support all of these device trees, ftp_cpu_setup()
should write the MAC address to mac-address and local-mac-address, if they
exist.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
commit a79886590593ba1d667c840caa4940c61639f18f
Author: Thomas Knobloch <knobloch@siemens.com>
Date: Sat May 5 07:04:42 2007 +0200
@ -919,12 +1411,35 @@ Date: Sun Apr 29 14:13:01 2007 +0200
Signed-off-by: Stefan Roese <sr@denx.de>
commit 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9
Author: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
Date: Sun Apr 29 14:01:54 2007 +0200
[PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.
Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
commit 5c5d3242935cf3543af01142627494434834cf98
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Apr 25 12:34:38 2007 -0500
mpc83xx: minor fixups for 8313rdb introduction
commit ada4d40091f6ed4a4f0040e08d20db21967e4a67
Author: Ladislav Michl <ladis@linux-mips.org>
Date: Wed Apr 25 16:01:26 2007 +0200
[PATCH] simplify silent console
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Stefan Roese <sr@denx.de>
commit 144876a380f5756f57412caf74c1d6dc201dd796
Author: Michal Simek <monstr@monstr.eu>
Date: Tue Apr 24 23:01:02 2007 +0200
@ -1221,6 +1736,58 @@ Date: Mon Apr 16 14:31:55 2007 -0500
Signed-off-by: Scott Wood <scottwood@freescale.com>
commit 7fc4c71a143be8666d70803fb25ae60379c95622
Author: Stefan Roese <sr@denx.de>
Date: Mon Apr 23 15:39:59 2007 +0200
Fix file mode
Signed-off-by: Stefan Roese <sr@denx.de>
commit 38257988abfe74d459ca2ad748b109ca04e4efe1
Author: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Date: Mon Apr 23 15:30:39 2007 +0200
[PATCH] Avoid assigning PCI resources from zero address
If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE
core complains and IDE drivers fails to work. Also, assigning zero to a BAR
was illegal according to PCI 2.1 (the later revisions seem to have excluded the
sentence about "0" being considered an invalid address) -- so, use a reasonable
starting value of 0x1000 (that's what the most Linux archs are using).
Alternatively, one might have fixed the calls to pci_set_region() individually
(some code even seems to have taken care of this issue) but that would have
been a lot more work. :-)
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Stefan Roese <sr@denx.de>
commit afb903a2eb9436baa9270ccc0c27082d86497d89
Author: Jeffrey Mann <mannj@embeddedplanet.com>
Date: Mon Apr 23 14:00:11 2007 +0200
[patch] setenv(...) can delete environmentalvariables
update setenv() function so that entering a NULL value for the
variable's value will delete the environmental variable
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Acked-by: Stefan Roese <sr@denx.de>
commit 36f104e5caa747d568eff26b369565af57c2ffa6
Author: Mike Frysinger <vapier@gentoo.org>
Date: Mon Apr 23 13:54:24 2007 +0200
[patch] use unsigned char in smc91111 driver for mac
the v_mac variable in the smc91111 driver is declared as a signed char ...
this causes problems when one of the bytes in the MAC is "signed" like 0xE0
because when it gets printed out, you get a display like:
0xFFFFFFE0 and that's no good
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522
Author: Stefan Roese <sr@denx.de>
Date: Mon Apr 23 12:00:22 2007 +0200

1
MAINTAINERS
View File

@ -282,6 +282,7 @@ Stefan Roese <sr@denx.de>
bunbinga PPC405EP
ebony PPC440GP
katmai PPC440SPe
lwmon5 PPC440EPx
ocotea PPC440GX
p3p440 PPC440GP
pcs440ep PPC440EP

29
MAKEALL
View File

@ -83,15 +83,15 @@ LIST_4xx=" \
csb272 csb472 DASA_SIM DP405 \
DU405 ebony ERIC EXBITGEN \
G2000 HH405 HUB405 JSE \
KAREF katmai luan METROBOX \
MIP405 MIP405T ML2 ml300 \
ocotea OCRTC ORSG p3p440 \
PCI405 pcs440ep PIP405 PLU405 \
PMC405 PPChameleonEVB sbc405 sc3 \
sequoia sequoia_nand taishan VOH405 \
VOM405 W7OLMC W7OLMG walnut \
WUH405 XPEDITE1K yellowstone yosemite \
yucca \
KAREF katmai luan lwmon5 \
METROBOX MIP405 MIP405T ML2 \
ml300 ocotea OCRTC ORSG \
p3p440 PCI405 pcs440ep PIP405 \
PLU405 PMC405 PPChameleonEVB sbc405 \
sc3 sequoia sequoia_nand taishan \
VOH405 VOM405 W7OLMC W7OLMG \
walnut WUH405 XPEDITE1K yellowstone \
yosemite yucca \
"
#########################################################################
@ -150,6 +150,14 @@ LIST_85xx=" \
TQM8560 \
"
#########################################################################
## MPC86xx Systems
#########################################################################
LIST_86xx=" \
MPC8641HPCN \
"
#########################################################################
## 74xx/7xx Systems
#########################################################################
@ -170,6 +178,7 @@ LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8220} ${LIST_824x} ${LIST_8260} \
${LIST_83xx} \
${LIST_85xx} \
${LIST_86xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
@ -356,7 +365,7 @@ do
microblaze| \
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do

14
Makefile
View File

@ -216,6 +216,8 @@ LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \
"post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi)
LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
@ -247,7 +249,7 @@ __LIBS := $(subst $(obj),,$(LIBS))
#########################################################################
#########################################################################
ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
all: $(ALL)
@ -267,6 +269,9 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
./tools/ubsha1 $(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
@ -1141,6 +1146,9 @@ katmai_config: unconfig
luan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
lwmon5_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
METROBOX_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
@ -2469,7 +2477,7 @@ clean:
$(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
$(obj)examples/test_burst
rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
$(obj)tools/gen_eth_addr
$(obj)tools/gen_eth_addr $(obj)tools/ubsha1
rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
@ -2492,7 +2500,7 @@ clobber: clean
rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
rm -fr $(obj)*.*~
rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c
rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
[ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f

79
README
View File

@ -1704,28 +1704,69 @@ The following options need to be configured:
-31 post/post.c POST test failed, detected by post_output_backlog()
-32 post/post.c POST test failed, detected by post_run_single()
-1 common/cmd_doc.c Bad usage of "doc" command
-1 common/cmd_doc.c No boot device
-1 common/cmd_doc.c Unknown Chip ID on boot device
-1 common/cmd_doc.c Read Error on boot device
-1 common/cmd_doc.c Image header has bad magic number
34 common/cmd_doc.c before loading a Image from a DOC device
-35 common/cmd_doc.c Bad usage of "doc" command
35 common/cmd_doc.c correct usage of "doc" command
-36 common/cmd_doc.c No boot device
36 common/cmd_doc.c correct boot device
-37 common/cmd_doc.c Unknown Chip ID on boot device
37 common/cmd_doc.c correct chip ID found, device available
-38 common/cmd_doc.c Read Error on boot device
38 common/cmd_doc.c reading Image header from DOC device OK
-39 common/cmd_doc.c Image header has bad magic number
39 common/cmd_doc.c Image header has correct magic number
-40 common/cmd_doc.c Error reading Image from DOC device
40 common/cmd_doc.c Image header has correct magic number
41 common/cmd_ide.c before loading a Image from a IDE device
-42 common/cmd_ide.c Bad usage of "ide" command
42 common/cmd_ide.c correct usage of "ide" command
-43 common/cmd_ide.c No boot device
43 common/cmd_ide.c boot device found
-44 common/cmd_ide.c Device not available
44 common/cmd_ide.c Device available
-45 common/cmd_ide.c wrong partition selected
45 common/cmd_ide.c partition selected
-46 common/cmd_ide.c Unknown partition table
46 common/cmd_ide.c valid partition table found
-47 common/cmd_ide.c Invalid partition type
47 common/cmd_ide.c correct partition type
-48 common/cmd_ide.c Error reading Image Header on boot device
48 common/cmd_ide.c reading Image Header from IDE device OK
-49 common/cmd_ide.c Image header has bad magic number
49 common/cmd_ide.c Image header has correct magic number
-50 common/cmd_ide.c Image header has bad checksum
50 common/cmd_ide.c Image header has correct checksum
-51 common/cmd_ide.c Error reading Image from IDE device
51 common/cmd_ide.c reading Image from IDE device OK
52 common/cmd_nand.c before loading a Image from a NAND device
-53 common/cmd_nand.c Bad usage of "nand" command
53 common/cmd_nand.c correct usage of "nand" command
-54 common/cmd_nand.c No boot device
54 common/cmd_nand.c boot device found
-55 common/cmd_nand.c Unknown Chip ID on boot device
55 common/cmd_nand.c correct chip ID found, device available
-56 common/cmd_nand.c Error reading Image Header on boot device
56 common/cmd_nand.c reading Image Header from NAND device OK
-57 common/cmd_nand.c Image header has bad magic number
57 common/cmd_nand.c Image header has correct magic number
-58 common/cmd_nand.c Error reading Image from NAND device
58 common/cmd_nand.c reading Image from NAND device OK
-1 common/cmd_ide.c Bad usage of "ide" command
-1 common/cmd_ide.c No boot device
-1 common/cmd_ide.c Unknown boot device
-1 common/cmd_ide.c Unknown partition table
-1 common/cmd_ide.c Invalid partition type
-1 common/cmd_ide.c Read Error on boot device
-1 common/cmd_ide.c Image header has bad magic number
-60 common/env_common.c Environment has a bad CRC, using default
-1 common/cmd_nand.c Bad usage of "nand" command
-1 common/cmd_nand.c No boot device
-1 common/cmd_nand.c Unknown Chip ID on boot device
-1 common/cmd_nand.c Read Error on boot device
-1 common/cmd_nand.c Image header has bad magic number
-1 common/env_common.c Environment has a bad CRC, using default
64 net/eth.c starting with Ethernetconfiguration.
-64 net/eth.c no Ethernet found.
65 net/eth.c Ethernet found.
-80 common/cmd_net.c usage wrong
80 common/cmd_net.c before calling NetLoop()
-81 common/cmd_net.c some error in NetLoop() occured
81 common/cmd_net.c NetLoop() back without error
-82 common/cmd_net.c size == 0 (File with size 0 loaded)
82 common/cmd_net.c trying automatic boot
83 common/cmd_net.c running autoscript
-83 common/cmd_net.c some error in automatic boot or autoscript
84 common/cmd_net.c end without errors
Modem Support:
--------------

2
board/amcc/acadia/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o
COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

16
board/amcc/acadia/acadia.c
View File

@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
@ -55,10 +55,12 @@ int board_early_init_f(void)
{
unsigned int reg;
#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
acadia_gpio_init();

11
board/amcc/acadia/memory.c
View File

@ -31,6 +31,8 @@
#include <asm/io.h>
#include <asm/gpio.h>
extern void board_pll_init_f(void);
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val)
long int initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;

0
board/amcc/acadia/cpr.c → board/amcc/acadia/pll.c
View File

4
board/amcc/bamboo/bamboo.c
View File

@ -416,7 +416,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -457,7 +457,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

8
board/amcc/ebony/ebony.c
View File

@ -207,14 +207,14 @@ long int fixed_sdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if ((strap & 0x00100000) == 0) {
@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/katmai/katmai.c
View File

@ -292,7 +292,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -309,7 +309,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/luan/luan.c
View File

@ -161,7 +161,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init( struct pci_controller *hose )
{
unsigned long strap;
@ -179,7 +179,7 @@ int pci_pre_init( struct pci_controller *hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************

4
board/amcc/ocotea/ocotea.c
View File

@ -306,7 +306,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

2
board/amcc/sequoia/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o sdram.o
COBJS = $(BOARD).o cmd_sequoia.o sdram.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

111
board/amcc/sequoia/cmd_sequoia.c 100644
View File

@ -0,0 +1,111 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
static u8 boot_533_nor[] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
};
static u8 boot_533_nand[] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
};
static u8 boot_667_nor[] = {
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
};
static u8 boot_667_nand[] = {
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 chip;
u8 *buf;
int cpu_freq;
if (argc < 3) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
cpu_freq = simple_strtol(argv[1], NULL, 10);
if (!((cpu_freq == 533) || (cpu_freq == 667))) {
printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
return 1;
}
/* use 0x52 as I2C EEPROM address for now */
chip = 0x52;
if ((strcmp(argv[2], "nor") != 0) &&
(strcmp(argv[2], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
if (strcmp(argv[2], "nand") == 0) {
switch (cpu_freq) {
default:
case 533:
buf = boot_533_nand;
break;
case 667:
buf = boot_667_nand;
break;
}
} else {
switch (cpu_freq) {
default:
case 533:
buf = boot_533_nor;
break;
case 667:
buf = boot_667_nor;
break;
}
}
if (i2c_write(chip, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", chip);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
return 0;
}
U_BOOT_CMD(
bootstrap, 3, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n",
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
);

36
board/amcc/sequoia/sequoia.c
View File

@ -25,7 +25,6 @@
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
#include "sequoia.h"
DECLARE_GLOBAL_DATA_PTR;
@ -226,7 +225,7 @@ int misc_init_r(void)
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
@ -254,7 +253,7 @@ int misc_init_r(void)
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
@ -298,7 +297,7 @@ int misc_init_r(void)
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@ -323,7 +322,7 @@ int misc_init_r(void)
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets*/
@ -426,23 +425,10 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
#if 0
/*--------------------------------------------------------------------------+
* Cactus is always configured as the host & requires the
* PCI arbiter to be enabled ???
*--------------------------------------------------------------------------*/
unsigned long strap;
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
#endif
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
@ -480,7 +466,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
@ -586,3 +572,13 @@ int is_pci_host(struct pci_controller *hose)
return (1);
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */

67
board/amcc/sequoia/sequoia.h
View File

@ -1,67 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*----------------------------------------------------------------------------+
| EBC Configuration Register - EBC0_CFG
+----------------------------------------------------------------------------*/
/* External Bus Three-State Control */
#define EBC0_CFG_EBTC_DRIVEN 0x80000000
/* Device-Paced Time-out Disable */
#define EBC0_CFG_PTD_ENABLED 0x00000000
/* Ready Timeout Count */
#define EBC0_CFG_RTC_MASK 0x38000000
#define EBC0_CFG_RTC_16PERCLK 0x00000000
#define EBC0_CFG_RTC_32PERCLK 0x08000000
#define EBC0_CFG_RTC_64PERCLK 0x10000000
#define EBC0_CFG_RTC_128PERCLK 0x18000000
#define EBC0_CFG_RTC_256PERCLK 0x20000000
#define EBC0_CFG_RTC_512PERCLK 0x28000000
#define EBC0_CFG_RTC_1024PERCLK 0x30000000
#define EBC0_CFG_RTC_2048PERCLK 0x38000000
/* External Master Priority Low */
#define EBC0_CFG_EMPL_LOW 0x00000000
#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
#define EBC0_CFG_EMPL_HIGH 0x06000000
/* External Master Priority High */
#define EBC0_CFG_EMPH_LOW 0x00000000
#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
#define EBC0_CFG_EMPH_HIGH 0x01800000
/* Chip Select Three-State Control */
#define EBC0_CFG_CSTC_DRIVEN 0x00400000
/* Burst Prefetch */
#define EBC0_CFG_BPF_ONEDW 0x00000000
#define EBC0_CFG_BPF_TWODW 0x00100000
#define EBC0_CFG_BPF_FOURDW 0x00200000
/* External Master Size */
#define EBC0_CFG_EMS_8BIT 0x00000000
/* Power Management Enable */
#define EBC0_CFG_PME_DISABLED 0x00000000
#define EBC0_CFG_PME_ENABLED 0x00020000
/* Power Management Timer */
#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
#define SDR0_USB0 0x0320 /* USB Control Register */

4
board/amcc/taishan/taishan.c
View File

@ -236,7 +236,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -253,7 +253,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/yosemite/yosemite.c
View File

@ -385,7 +385,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/yucca/yucca.c
View File

@ -604,7 +604,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -621,7 +621,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

2
board/bf537-stamp/ether_bf537.c
View File

@ -48,7 +48,7 @@
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];

6
board/bf537-stamp/flash-defines.h
View File

@ -44,9 +44,9 @@
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

2
board/bf537-stamp/stm_m25p64.c
View File

@ -9,7 +9,7 @@
/* Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000

12
board/bf537-stamp/u-boot.lds.S
View File

@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
__DYNAMIC = 0; */
MEMORY
{
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
@ -47,11 +47,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@ -68,7 +68,7 @@ SECTIONS
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */

10
board/cds/mpc8548cds/mpc8548cds.c
View File

@ -345,23 +345,23 @@ int last_stage_init(void)
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 18);
miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_read(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, temp);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 3);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}

134
board/esd/cpci405/cpci405.c
View File

@ -23,13 +23,15 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
@ -52,8 +54,6 @@ const unsigned char fpgadata[] =
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
#include "../common/auto_update.h"
#ifdef CONFIG_CPCI405AB
@ -86,13 +86,11 @@ au_image_t au_image[] = {
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */
int cpci405_version(void);
int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f (void)
{
#ifndef CONFIG_CPCI405_VER2
@ -111,10 +109,10 @@ int board_early_init_f (void)
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
@ -176,47 +174,48 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
#else
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/* ------------------------------------------------------------------------- */
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
return 0; /* no, board is cpci405 */
return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
return 0; /* no, board is cpci405 */
return 0; /* no, board is cpci405 */
else
return -1; /* yes, board is cterm-m2 */
return -1; /* yes, board is cterm-m2 */
#endif
}
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
return -1; /* yes, board is cpci405 host */
return -1; /* yes, board is cpci405 host */
else
return 0; /* no, board is cpci405 adapter */
return 0; /* no, board is cpci405 adapter */
}
int cpci405_version(void)
{
unsigned long cntrl0Reg;
@ -227,10 +226,10 @@ int cpci405_version(void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
@ -245,7 +244,7 @@ int cpci405_version(void)
/* CS2==0 && CS3==1 -> version 2 */
return 2;
case 0x00100000:
/* CS2==1 && CS3==0 -> version 3 */
/* CS2==1 && CS3==0 -> version 3 or 6U board */
return 3;
case 0x00000000:
/* CS2==0 && CS3==0 -> version 4 */
@ -256,13 +255,11 @@ int cpci405_version(void)
}
}
int misc_init_f (void)
{
return 0; /* dummy implementation */
}
int misc_init_r (void)
{
unsigned long cntrl0Reg;
@ -283,7 +280,6 @@ int misc_init_r (void)
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
@ -354,6 +350,7 @@ int misc_init_r (void)
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
@ -375,6 +372,7 @@ int misc_init_r (void)
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
@ -425,7 +423,6 @@ int misc_init_r (void)
return (0);
}
/*
* Check Board Identity:
*/
@ -481,7 +478,7 @@ int checkboard (void)
}
#ifndef CONFIG_CPCI405_VER2
puts ("\nFPGA: ");
puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
@ -493,12 +490,6 @@ int checkboard (void)
#endif
putc ('\n');
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
return 0;
}
@ -511,22 +502,18 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
void reset_phy(void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
#ifdef CONFIG_LXT971_NO_SLEEP
return (0);
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}
/* ------------------------------------------------------------------------- */
@ -551,14 +538,47 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */
#if defined(CONFIG_PCI)
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line = 0xff;
/*
* Write pci interrupt line register (cpci405 specific)
*/
switch (PCI_DEV(dev) & 0x03) {
case 0:
int_line = 27 + 2;
break;
case 1:
int_line = 27 + 3;
break;
case 2:
int_line = 27 + 0;
break;
case 3:
int_line = 27 + 1;
break;
}
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
int pci_pre_init(struct pci_controller *hose)
{
hose->fixup_irq = cpci405_pci_fixup_irq;
return 1;
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_CPCI405AB
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|= CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
&= ~CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
& CFG_FPGA_MODE_1WIRE)
/*
@ -581,7 +601,6 @@ int OWTouchReset(void)
return result;
}
/*
* Send 1 a 1-wire write bit.
* Provide 10us recovery time.
@ -607,7 +626,6 @@ void OWWriteBit(int bit)
}
}
/*
* Read a bit from the 1-wire bus and return it.
* Provide 10us recovery time.
@ -627,7 +645,6 @@ int OWReadBit(void)
return result;
}
void OWWriteByte(int data)
{
int loop;
@ -638,7 +655,6 @@ void OWWriteByte(int data)
}
}
int OWReadByte(void)
{
int loop, result = 0;
@ -653,7 +669,6 @@ int OWReadByte(void)
return result;
}
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned short val;
@ -694,7 +709,6 @@ U_BOOT_CMD(
NULL
);
#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/

1
board/hermes/hermes.c
View File

@ -597,6 +597,7 @@ void show_boot_progress (int status)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
if (status < -32) status = -1; /* let things compatible */
status ^= 0x0F;
status = (status & 0x0F) << 14;
immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;

1
board/logodl/logodl.c
View File

@ -107,6 +107,7 @@ void logodl_set_led(int led, int state)
void show_boot_progress (int status)
{
if (status < -32) status = -1; /* let things compatible */
/*
switch(status) {
case 1: logodl_set_led(0,1); break;

51
board/lwmon5/Makefile 100644
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o sdram.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

39
board/lwmon5/config.mk 100644
View File

@ -0,0 +1,39 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# lwmon5 (440EPx)
#
ifndef TEXT_BASE
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

90
board/lwmon5/init.S 100644
View File

@ -0,0 +1,90 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
/* TLB-entry for PCI Memory */
tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for the FPGA Chip select 2 */
tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
/* TLB-entry for the FPGA Chip select 3 */
tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
/* TLB-entry for the LIME Controller */
tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
/* TLB-entry for Internal Registers & OCM */
tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I)
/*TLB-entry PCI registers*/
tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry for peripherals */
tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end

465
board/lwmon5/lwmon5.c 100644
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@ -0,0 +1,465 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc440.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (ulong base, int banknum);
int board_early_init_f(void)
{
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
/* PLB Write pipelining disabled. Denali Core workaround */
mtdcr(plb0_acr, 0xDE000000);
mtdcr(plb1_acr, 0xDE000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
/* Trace Pins are disabled. SDR0_PFC0 Register */
mtsdr(SDR0_PFC0, 0x0);
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
/* SMII via ZMII */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_6;
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_6;
/* enable SPI (SCP) */
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_PFC4, 0x80000000);
/* PCI arbiter disabled */
/* PCI Host Configuration disbaled */
mfsdr(sdr_pci0, reg);
reg = 0;
mtsdr(sdr_pci0, 0x00000000 | reg);
gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
return 0;
}
/*---------------------------------------------------------------------------+
| misc_init_r.
+---------------------------------------------------------------------------*/
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mfebc(pb0cr, pbcr);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(pb0cr, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
/*
* USB suff...
*/
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*
* Clear resets
*/
udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay (1000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
/*
* Reset Lime controller
*/
gpio_write_bit(CFG_GPIO_LIME_S, 1);
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
/* Lime memory clock adjusted to 133MHz */
out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
/* Wait untill time expired. Because of requirements in lime manual */
udelay(300);
/* Write lime controller memory parameters */
out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
/*
* Reset PHY's
*/
gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
return 0;
}
int checkboard(void)
{
char *s = getenv("serial#");
printf("Board: lwmon5");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_MBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Cactus is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
void hw_watchdog_reset(void)
{
int val;
/*
* Toggle watchdog output
*/
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
}

662
board/lwmon5/sdram.c 100644
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/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <ppc440.h>
#include "sdram.h"
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
* EMAC driver, that need it's buffer descriptor to be located in non cached
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CFG_ENABLE_SDRAM_CACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);
#ifdef CONFIG_ADD_RAM_INFO
static u32 is_ecc_enabled(void)
{
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;
if (val)
return 1;
else
return 0;
}
void board_add_ram_info(int use_default)
{
PPC440_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())
puts(" (ECC");
else
puts(" (ECC not");
get_sys_info(&board_cfg);
printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
printf(", CL%d)", val);
}
#endif
static int wait_for_dlllock(void)
{
u32 val;
int wait = 0;
/*
* Wait for the DCC master delay line to finish calibration
*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
#if defined(CONFIG_DDR_DATA_EYE)
int wait_for_dram_init_complete(void)
{
u32 val;
int wait = 0;
/*
* Wait for 'DRAM initialization complete' bit in status register
*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
#define NUM_TRIES 64
#define NUM_READS 10
void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)start_addr;
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/*
* Set 'wr_dqs_shift'
*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/*
* Set 'dqs_out_shift' = wr_dqs_shift + 32
*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/*
* Set 'dll_dqs_delay_X'.
*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Wait for the DCC master delay line to finish calibration
*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/*
* Largest passing window is now detected.
*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/*
* De-assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/*
* Set 'wr_dqs_shift'
*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/*
* Set 'dqs_out_shift' = wr_dqs_shift + 32
*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/*
* Set 'dll_dqs_delay_X'.
*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/*
* Assert 'start' parameter.
*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/*
* Wait for the DCC master delay line to finish calibration
*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */
#ifdef CONFIG_DDR_ECC
static void wait_ddr_idle(void)
{
/*
* Controller idle status cannot be determined for Denali
* DDR2 code. Just return here.
*/
}
static void blank_string(int size)
{
int i;
for (i=0; i<size; i++)
putc('\b');
for (i=0; i<size; i++)
putc(' ');
for (i=0; i<size; i++)
putc('\b');
}
static void program_ecc(u32 start_address,
u32 num_bytes,
u32 tlb_word2_i_value)
{
u32 current_address;
u32 end_address;
u32 address_increment;
u32 val;
char str[] = "ECC generation -";
char slash[] = "\\|/-\\|/-";
int loop = 0;
int loopi = 0;
current_address = start_address;
sync();
eieio();
wait_ddr_idle();
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
/* ECC bit set method for non-cached memory */
address_increment = 4;
end_address = current_address + num_bytes;
puts(str);
while (current_address < end_address) {
*((u32 *)current_address) = 0x00000000;
current_address += address_increment;
if ((loop++ % (2 << 20)) == 0) {
putc('\b');
putc(slash[loopi++ % 8]);
}
}
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
* Therefore we don't fill the memory with a pattern or
* just zero it, but write the same values back that are
* already in the memory cells.
*/
address_increment = CFG_CACHELINE_SIZE;
end_address = current_address + num_bytes;
current_address = start_address;
while (current_address < end_address) {
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
}
#else
dcbz_area(start_address, num_bytes);
dflush();
#endif
}
sync();
eieio();
wait_ddr_idle();
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
sync();
eieio();
wait_ddr_idle();
}
#endif
static __inline__ u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static __inline__ void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
{
u32 val;
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
mtsdram(DDR0_04, 0x0A030300);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0103C812);
mtsdram(DDR0_07, 0x00090100);
mtsdram(DDR0_08, 0x02c80001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x000CC800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x1e000000);
mtsdram(DDR0_18, 0x1e1e1e1e);
mtsdram(DDR0_19, 0x1e1e1e1e);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
#ifdef CONFIG_DDR_ECC
mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
#else
mtsdram(DDR0_22, 0x00267F0B);
#endif
mtsdram(DDR0_23, 0x01000000);
mtsdram(DDR0_24, 0x01010001);
mtsdram(DDR0_26, 0x2D93028A);
mtsdram(DDR0_27, 0x0784682B);
mtsdram(DDR0_28, 0x00000080);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000006);
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#else
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
mtsdram(DDR0_04, 0x0B030300);
mtsdram(DDR0_05, 0x02020308);
mtsdram(DDR0_06, 0x0003C812);
mtsdram(DDR0_07, 0x00090100);
mtsdram(DDR0_08, 0x03c80001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x000CC800);
mtsdram(DDR0_12, 0x00000003);
mtsdram(DDR0_14, 0x00000000);
mtsdram(DDR0_17, 0x1e000000);
mtsdram(DDR0_18, 0x1e1e1e1e);
mtsdram(DDR0_19, 0x1e1e1e1e);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
#ifdef CONFIG_DDR_ECC
mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
#else
mtsdram(DDR0_22, 0x00267F0B);
#endif
mtsdram(DDR0_23, 0x01000000);
mtsdram(DDR0_24, 0x01010001);
mtsdram(DDR0_26, 0x2D93028A);
mtsdram(DDR0_27, 0x0784682B);
mtsdram(DDR0_28, 0x00000080);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000008);
mtsdram(DDR0_43, 0x050A0200);
mtsdram(DDR0_44, 0x00000005);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#endif
wait_for_dlllock();
/*
* Program tlb entries for this size (dynamic)
*/
program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation.
*/
program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#ifdef CONFIG_DDR_DATA_EYE
/*
* Perform data eye search if requested.
*/
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
val = get_mcsr();
set_mcsr(val);
#endif
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#endif
return (CFG_MBYTES_SDRAM << 20);
}

505
board/lwmon5/sdram.h 100644
View File

@ -0,0 +1,505 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_
#define ppcMsync sync
#define ppcMbar eieio
/* General definitions */
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
#define MAXRANKS 2 /* 2 ranks maximum */
/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ 133333333
#define PLB_FREQ_152MHZ 152000000
#define PLB_FREQ_160MHZ 160000000
#define PLB_FREQ_166MHZ 166666666
/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
/*-----------------------------------------------------------------------------+
| Values for ddrcfga register - indirect addressing of these regs
+-----------------------------------------------------------------------------*/
#define DDR0_00 0x00
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0 0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1 0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2 0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3 0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4 0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5 0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6 0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7 0x00800000
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_02 0x02
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK 0x00000001
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF 0x00000000
#define DDR0_02_START_ON 0x00000001
#define DDR0_03 0x03
#define DDR0_03_BSTLEN_MASK 0x07000000
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK 0x00070000
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK 0x0000000F
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_04 0x04
#define DDR0_04_TRC_MASK 0x1F000000
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK 0x00070000
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK 0x00000700
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_05 0x05
#define DDR0_05_TMRD_MASK 0x1F000000
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK 0x00070000
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK 0x00000F00
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_06 0x06
#define DDR0_06_WRITEINTERP_MASK 0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK 0x00070000
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK 0x0000007F
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_07 0x07
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK 0x001F0000
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK 0x00000001
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_08 0x08
#define DDR0_08_WRLAT_MASK 0x07000000
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK 0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_09 0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK 0x00030000
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_10 0x0A
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK 0x00000300
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
#define DDR0_11 0x0B
#define DDR0_11_SREFRESH_MASK 0x01000000
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK 0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_12 0x0C
#define DDR0_12_TCKE_MASK 0x0000007
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK 0x00010000
#define DDR0_14_REDUC_64BITS 0x00000000
#define DDR0_14_REDUC_32BITS 0x00010000
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18 0x12
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_19 0x13
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_20 0x14
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_21 0x15
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_24 0x18
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
#define DDR0_25 0x19
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_26 0x1A
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_27_TINIT_MASK 0x0000FFFF
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_28 0x1C
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_32 0x20
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_33 0x21
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_34 0x22
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_35 0x23
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_36 0x24
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_37 0x25
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_38 0x26
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_39 0x27
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_40 0x28
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_41 0x29
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_42 0x2A
#define DDR0_42_ADDR_PINS_MASK 0x07000000
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_43 0x2B
#define DDR0_43_TWR_MASK 0x07000000
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_43_APREBIT_MASK 0x000F0000
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_44 0x2C
#define DDR0_44_TRCD_MASK 0x000000FF
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#endif /* _SPD_SDRAM_DENALI_H_ */

145
board/lwmon5/u-boot.lds 100644
View File

@ -0,0 +1,145 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

3
board/pcs440ep/config.mk
View File

@ -25,6 +25,9 @@
# PCS440EP board
#
# Check the U-Boot Image with a SHA1 checksum
ALL += $(obj)u-boot.sha1
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)

4
board/pcs440ep/flash.c
View File

@ -83,6 +83,7 @@ void flash_print_info(flash_info_t *info)
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
case FLASH_MAN_MX: printf ("MXIC "); break;
default: printf ("Unknown Vendor "); break;
}
@ -195,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
info->flash_id = FLASH_MAN_EXCEL;
break;
case (CFG_FLASH_WORD_SIZE)MX_MANUFACT:
info->flash_id = FLASH_MAN_MX;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;

41
board/pcs440ep/init.S
View File

@ -87,27 +87,32 @@
.globl tlbtab
tlbtab:
tlbtab_start
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR detection
* routine.
*/
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

499
board/pcs440ep/pcs440ep.c
View File

@ -23,20 +23,112 @@
#include <common.h>
#include <ppc4xx.h>
#include <malloc.h>
#include <command.h>
#include <crc.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <status_led.h>
#include <sha1.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static void set_leds(int val)
unsigned char sha1_checksum[SHA1_SUM_LEN];
/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
static void set_leds (int val)
{
unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
}
#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
void __led_init (led_id_t mask, int state)
{
int val = GET_LEDS;
if (state == STATUS_LED_ON)
val |= mask;
else
val &= ~mask;
set_leds (val);
}
void __led_set (led_id_t mask, int state)
{
int val = GET_LEDS;
if (state == STATUS_LED_ON)
val |= mask;
else if (state == STATUS_LED_OFF)
val &= ~mask;
set_leds (val);
}
void __led_toggle (led_id_t mask)
{
int val = GET_LEDS;
val ^= mask;
set_leds (val);
}
static void status_led_blink (void)
{
int i;
int val = GET_LEDS;
/* set all LED which are on, to state BLINKING */
for (i = 0; i < 4; i++) {
if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING);
val = val << 1;
}
}
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress (int val)
{
/* find all valid Codes for val in README */
if (val == -30) return;
if (val < 0) {
/* smthing goes wrong */
status_led_blink ();
return;
}
switch (val) {
case 1:
/* validating Image */
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_ON);
status_led_set (2, STATUS_LED_ON);
break;
case 15:
/* booting */
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_ON);
status_led_set (2, STATUS_LED_ON);
break;
case 64:
/* starting Ethernet configuration */
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_OFF);
status_led_set (2, STATUS_LED_ON);
break;
case 80:
/* loading Image */
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_OFF);
status_led_set (2, STATUS_LED_ON);
break;
}
}
#endif
int board_early_init_f(void)
{
register uint reg;
@ -85,6 +177,251 @@ int board_early_init_f(void)
return 0;
}
#define EEPROM_LEN 256
void load_sernum_ethaddr (void)
{
int ret;
char buf[EEPROM_LEN];
char mac[32];
char *use_eeprom;
u16 checksumcrc16 = 0;
/* read the MACs from EEprom */
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_ON);
ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
if (ret == 0) {
checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
/* check, if the EEprom is programmed:
* - The Prefix(Byte 0,1,2) is equal to "ATR"
* - The checksum, stored in the last 2 Bytes, is correct
*/
if ((strncmp (buf,"ATR",3) != 0) ||
((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
/* EEprom is not programmed */
printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
} else {
/* get the MACs */
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
buf[3],
buf[4],
buf[5],
buf[6],
buf[7],
buf[8]);
setenv ("ethaddr", (char *) mac);
sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
buf[9],
buf[10],
buf[11],
buf[12],
buf[13],
buf[14]);
setenv ("eth1addr", (char *) mac);
return;
}
}
/* some error reading the EEprom */
if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
/* dont use bootcmd */
setenv("bootdelay", "-1");
return;
}
/* == default ? use standard */
if (strncmp (use_eeprom, "default", 7) == 0) {
return;
}
/* Env doesnt exist -> hang */
status_led_blink ();
hang ();
return;
}
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
struct kbd_data_t {
char s1;
char s2;
};
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
{
char *val;
unsigned long tmp;
/* use the DIPs for some bootoptions */
val = getenv (ENV_NAME_DIP);
tmp = simple_strtoul (val, NULL, 16);
kbd_data->s2 = (tmp & 0x0f);
kbd_data->s1 = (tmp & 0xf0) >> 4;
return kbd_data;
}
static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
{
char s1 = str[0];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s1) return -1;
s1 = str[1];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s2) return -1;
return 0;
}
static char *key_match (const struct kbd_data_t *kbd_data)
{
char magic[sizeof (kbd_magic_prefix) + 1];
char *suffix;
char *kbd_magic_keys;
/*
* The following string defines the characters that can be appended
* to "key_magic" to form the names of environment variables that
* hold "magic" key codes, i. e. such key codes that can cause
* pre-boot actions. If the string is empty (""), then only
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
kbd_magic_keys = "";
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys; *suffix ||
suffix == kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
if (compare_magic (kbd_data, getenv (magic)) == 0) {
char cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv (cmd_name);
return (cmd);
}
}
return (NULL);
}
#endif /* CONFIG_PREBOOT */
static int pcs440ep_readinputs (void)
{
int i;
char value[20];
/* read the inputs and set the Envvars */
/* Revision Level Bit 26 - 29 */
i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
i = swapbits[i];
sprintf (value, "%02x", i);
setenv (ENV_NAME_REVLEV, value);
/* Solder Switch Bit 30 - 33 */
i = (in32 (GPIO0_IR) & 0x00000003) << 2;
i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
i = swapbits[i];
sprintf (value, "%02x", i);
setenv (ENV_NAME_SOLDER, value);
/* DIP Switch Bit 49 - 56 */
i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
sprintf (value, "%02x", i);
setenv (ENV_NAME_DIP, value);
return 0;
}
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
/*************************************************************************
* calculate a SHA1 sum for the U-Boot image in Flash.
*
************************************************************************/
static int pcs440ep_sha1 (int docheck)
{
unsigned char *data;
unsigned char *ptroff;
unsigned char output[20];
unsigned char org[20];
int i, len = CONFIG_SHA1_LEN;
memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
data = (unsigned char *)CFG_LOAD_ADDR;
ptroff = &data[len + SHA1_SUM_POS];
for (i = 0; i < SHA1_SUM_LEN; i++) {
org[i] = ptroff[i];
ptroff[i] = 0;
}
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
if (docheck == 2) {
for (i = 0; i < 20 ; i++) {
printf("%02X ", output[i]);
}
printf("\n");
}
if (docheck == 1) {
for (i = 0; i < 20 ; i++) {
if (org[i] != output[i]) return 1;
}
}
return 0;
}
/*************************************************************************
* do some checks after the SHA1 checksum from the U-Boot Image was
* calculated.
*
************************************************************************/
static void pcs440ep_checksha1 (void)
{
int ret;
char *cs_test;
ret = pcs440ep_sha1 (1);
if (ret == 0) return;
if ((cs_test = getenv ("cs_test")) == NULL) {
/* Env doesnt exist -> hang */
status_led_blink ();
hang ();
}
if (strncmp (cs_test, "off", 3) == 0) {
printf ("SHA1 U-Boot sum NOT ok!\n");
setenv ("bootdelay", "-1");
}
}
#else
static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
#endif
int misc_init_r (void)
{
uint pbcr;
@ -139,6 +476,18 @@ int misc_init_r (void)
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[1]);
pcs440ep_readinputs ();
pcs440ep_checksha1 ();
#ifdef CONFIG_PREBOOT
{
struct kbd_data_t kbd_data;
/* Decode keys */
char *str = strdup (key_match (get_keys (&kbd_data)));
/* Set or delete definition */
setenv ("preboot", str);
free (str);
}
#endif /* CONFIG_PREBOOT */
return 0;
}
@ -156,13 +505,31 @@ int checkboard(void)
return (0);
}
void spd_ddr_init_hang (void)
{
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_ON);
/* we cannot use hang() because we are still running from
Flash, and so the status_led driver is not initialized */
puts ("### ERROR ### Please RESET the board ###\n");
for (;;) {
__led_toggle (4);
udelay (100000);
}
}
long int initdram (int board_type)
{
long dram_size = 0;
set_leds(1); /* display boot info counter */
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_OFF);
dram_size = spd_sdram();
set_leds(2); /* display boot info counter */
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_ON);
if (dram_size == 0) {
hang();
}
return dram_size;
}
@ -217,7 +584,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -258,7 +625,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
@ -377,3 +744,119 @@ void hw_watchdog_reset(void)
}
#endif
/*************************************************************************
* "led" Commando for the U-Boot shell
*
************************************************************************/
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
ulong pattern = 0;
pattern = simple_strtoul (argv[1], NULL, 10);
if (pattern > 200) {
status_led_blink ();
hang ();
return rcode;
}
if (pattern > 100) {
status_led_blink ();
return rcode;
}
pattern &= 0x0f;
set_leds (pattern);
return rcode;
}
U_BOOT_CMD(
led, 2, 1, do_led,
"led - set the led\n",
NULL
);
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
/*************************************************************************
* "sha1" Commando for the U-Boot shell
*
************************************************************************/
int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = -1;
if (argc < 2) {
usage:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (argc >= 3) {
unsigned char *data;
unsigned char output[20];
int len;
int i;
data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
len = simple_strtoul (argv[2], NULL, 16);
sha1_csum (data, len, (unsigned char *)output);
printf ("U-Boot sum:\n");
for (i = 0; i < 20 ; i++) {
printf ("%02X ", output[i]);
}
printf ("\n");
if (argc == 4) {
data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
memcpy (data, output, 20);
}
return 0;
}
if (argc == 2) {
char *ptr = argv[1];
if (*ptr != '-') goto usage;
ptr++;
if ((*ptr == 'c') || (*ptr == 'C')) {
rcode = pcs440ep_sha1 (1);
printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
} else if ((*ptr == 'p') || (*ptr == 'P')) {
rcode = pcs440ep_sha1 (2);
} else {
rcode = pcs440ep_sha1 (0);
}
return rcode;
}
return rcode;
}
U_BOOT_CMD(
sha1, 4, 1, do_sha1,
"sha1 - calculate the SHA1 Sum\n",
"address len [addr] calculate the SHA1 sum [save at addr]\n"
" -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
" -c check the U-Boot image in flash\n"
);
#endif
#ifdef CONFIG_IDE_PREINIT
int ide_preinit (void)
{
/* Set True IDE Mode */
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
udelay (100000);
return 0;
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset == 0) {
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
} else {
out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
}
udelay (10000);
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */

1
board/pcs440ep/u-boot.lds
View File

@ -65,6 +65,7 @@ SECTIONS
{
cpu/ppc4xx/start.o (.text)
board/pcs440ep/init.o (.text)
lib_generic/sha1.o (.text)
*(.text)
*(.fixup)

4
board/prodrive/alpr/alpr.c
View File

@ -172,7 +172,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -192,7 +192,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/prodrive/p3p440/p3p440.c
View File

@ -176,7 +176,7 @@ int misc_init_r (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/sandburst/common/sb_common.c
View File

@ -313,7 +313,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

1
board/sc520_cdp/sc520_cdp.c
View File

@ -507,6 +507,7 @@ int dram_init(void)
void show_boot_progress(int val)
{
if (val < -32) val = -1; /* let things compatible */
outb(val&0xff, 0x80);
outb((val&0xff00)>>8, 0x680);
}

1
board/sc520_spunk/sc520_spunk.c
View File

@ -507,6 +507,7 @@ void show_boot_progress(int val)
{
int version = read_mmcr_byte(SC520_SYSINFO);
if (val < -32) val = -1; /* let things compatible */
if (version == 0) {
/* PIO31-PIO16 Data */
write_mmcr_word(SC520_PIODATA31_16,

2
board/smdk2400/lowlevel_init.S
View File

@ -117,7 +117,7 @@
#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
#define Trp 0x0 /* 2 clk */
#define Trc 0x3 /* 7 clk */
#define Tchr 0x2 /* 3 clk */
#define Tchr 0x2 /* 3 clk */
#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */

274
board/stxssa/stxssa.c
View File

@ -52,147 +52,147 @@ long int fixed_sdram (void);
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
@ -227,12 +227,12 @@ reset_phy(void)
#if (CONFIG_ETHER_INDEX == 2)
bcsr->bcsr2 &= ~FETH2_RST;
udelay(2);
bcsr->bcsr2 |= FETH2_RST;
bcsr->bcsr2 |= FETH2_RST;
udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
bcsr->bcsr3 &= ~FETH3_RST;
udelay(2);
bcsr->bcsr3 |= FETH3_RST;
bcsr->bcsr3 |= FETH3_RST;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
@ -252,10 +252,10 @@ int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile ccsr_pcix_t *pci = &immr->im_pcix;
pci->peer &= 0xfffffffdf; /* disable master abort */
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
/* Why is the phy reset done _after_ the ethernet

11
board/tqm5200/tqm5200.c
View File

@ -32,6 +32,10 @@
#include <pci.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#ifdef CONFIG_VIDEO_SM501
#include <sm501.h>
#endif
@ -775,3 +779,10 @@ int board_get_height (void)
}
#endif /* CONFIG_VIDEO_SM501 */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */

4
board/xpedite1k/xpedite1k.c
View File

@ -209,7 +209,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose )
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
common/Makefile
View File

@ -38,8 +38,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
cmd_usb.o cmd_vfd.o \
cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \

19
common/cmd_doc.c
View File

@ -216,6 +216,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
image_header_t *hdr;
int rcode = 0;
SHOW_BOOT_PROGRESS (34);
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
@ -236,24 +237,27 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-35);
return 1;
}
SHOW_BOOT_PROGRESS (35);
if (!boot_device) {
puts ("\n** No boot device **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-36);
return 1;
}
SHOW_BOOT_PROGRESS (36);
dev = simple_strtoul(boot_device, &ep, 16);
if ((dev >= CFG_MAX_DOC_DEVICE) ||
(doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) {
printf ("\n** Device %d not available\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-37);
return 1;
}
SHOW_BOOT_PROGRESS (37);
printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr,
@ -262,9 +266,10 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (doc_rw (doc_dev_desc + dev, 1, offset,
SECTORSIZE, NULL, (u_char *)addr)) {
printf ("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-38);
return 1;
}
SHOW_BOOT_PROGRESS (38);
hdr = (image_header_t *)addr;
@ -276,16 +281,18 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
cnt -= SECTORSIZE;
} else {
puts ("\n** Bad Magic Number **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-39);
return 1;
}
SHOW_BOOT_PROGRESS (39);
if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
NULL, (u_char *)(addr+SECTORSIZE))) {
printf ("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-40);
return 1;
}
SHOW_BOOT_PROGRESS (40);
/* Loading ok, update default load address */

60
common/cmd_ide.c
View File

@ -185,6 +185,9 @@ static void input_data(int dev, ulong *sect_buf, int words);
static void output_data(int dev, ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
#ifndef CFG_ATA_PORT_ADDR
#define CFG_ATA_PORT_ADDR(port) (port)
#endif
#ifdef CONFIG_ATAPI
static void atapi_inquiry(block_dev_desc_t *dev_desc);
@ -382,6 +385,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
image_header_t *hdr;
int rcode = 0;
SHOW_BOOT_PROGRESS (41);
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
@ -397,44 +401,50 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-42);
return 1;
}
SHOW_BOOT_PROGRESS (42);
if (!boot_device) {
puts ("\n** No boot device **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-43);
return 1;
}
SHOW_BOOT_PROGRESS (43);
dev = simple_strtoul(boot_device, &ep, 16);
if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) {
printf ("\n** Device %d not available\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-44);
return 1;
}
SHOW_BOOT_PROGRESS (44);
if (*ep) {
if (*ep != ':') {
puts ("\n** Invalid boot device, use `dev[:part]' **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-45);
return 1;
}
part = simple_strtoul(++ep, NULL, 16);
}
SHOW_BOOT_PROGRESS (45);
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-46);
return 1;
}
SHOW_BOOT_PROGRESS (46);
if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) &&
(strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-47);
return 1;
}
SHOW_BOOT_PROGRESS (47);
printf ("\nLoading from IDE device %d, partition %d: "
"Name: %.32s Type: %.32s\n",
@ -445,26 +455,29 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) {
printf ("** Read error on %d:%d\n", dev, part);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-48);
return 1;
}
SHOW_BOOT_PROGRESS (48);
hdr = (image_header_t *)addr;
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
printf("\n** Bad Magic Number **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-49);
return 1;
}
SHOW_BOOT_PROGRESS (49);
checksum = ntohl(hdr->ih_hcrc);
hdr->ih_hcrc = 0;
if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) {
puts ("\n** Bad Header Checksum **\n");
SHOW_BOOT_PROGRESS (-2);
SHOW_BOOT_PROGRESS (-50);
return 1;
}
SHOW_BOOT_PROGRESS (50);
hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */
print_image_hdr (hdr);
@ -477,9 +490,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt,
(ulong *)(addr+info.blksz)) != cnt) {
printf ("** Read error on %d:%d\n", dev, part);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-51);
return 1;
}
SHOW_BOOT_PROGRESS (51);
/* Loading ok, update default load address */
@ -807,13 +821,13 @@ ide_outb(int dev, int port, unsigned char val)
/* Ensure I/O operations complete */
EIEIO;
*((uchar *)(ATA_CURR_BASE(dev)+port)) = val;
*((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val;
}
#else /* ! __PPC__ */
static void __inline__
ide_outb(int dev, int port, unsigned char val)
{
outb(val, ATA_CURR_BASE(dev)+port);
outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
}
#endif /* __PPC__ */
@ -825,7 +839,7 @@ ide_inb(int dev, int port)
uchar val;
/* Ensure I/O operations complete */
EIEIO;
val = *((uchar *)(ATA_CURR_BASE(dev)+port));
val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)));
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
dev, port, (ATA_CURR_BASE(dev)+port), val);
return (val);
@ -834,7 +848,7 @@ ide_inb(int dev, int port)
static unsigned char __inline__
ide_inb(int dev, int port)
{
return inb(ATA_CURR_BASE(dev)+port);
return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port));
}
#endif /* __PPC__ */
@ -891,6 +905,9 @@ input_swap_data(int dev, ulong *sect_buf, int words)
#ifdef __MIPS__
*dbuf++ = swab16p((u16*)pbuf);
*dbuf++ = swab16p((u16*)pbuf);
#elif defined(CONFIG_PCS440EP)
*dbuf++ = *pbuf;
*dbuf++ = *pbuf;
#else
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
@ -930,10 +947,18 @@ output_data(int dev, ulong *sect_buf, int words)
pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
dbuf = (ushort *)sect_buf;
while (words--) {
#if defined(CONFIG_PCS440EP)
/* not tested, because CF was write protected */
EIEIO;
*pbuf = ld_le16(dbuf++);
EIEIO;
*pbuf = ld_le16(dbuf++);
#else
EIEIO;
*pbuf = *dbuf++;
EIEIO;
*pbuf = *dbuf++;
#endif
}
#endif
}
@ -981,10 +1006,17 @@ input_data(int dev, ulong *sect_buf, int words)
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
#if defined(CONFIG_PCS440EP)
EIEIO;
*dbuf++ = ld_le16(pbuf);
EIEIO;
*dbuf++ = ld_le16(pbuf);
#else
EIEIO;
*dbuf++ = *pbuf;
EIEIO;
*dbuf++ = *pbuf;
#endif
}
#endif
}

120
common/cmd_log.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2002-2007
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* Code used from linux/kernel/printk.c
@ -60,45 +60,40 @@ static char buf[1024];
/* This combination will not print messages with the default loglevel */
static unsigned console_loglevel = 3;
static unsigned default_message_loglevel = 4;
static unsigned char *log_buf = NULL;
static unsigned long *ext_log_size;
static unsigned long *ext_log_start;
static unsigned long *ext_logged_chars;
#define log_size (*ext_log_size)
#define log_start (*ext_log_start)
#define logged_chars (*ext_logged_chars)
static unsigned log_version = 1;
static logbuff_t *log;
/* Forced by code, eh! */
#define LOGBUFF_MAGIC 0xc0de4ced
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
void logbuff_init_ptrs (void)
{
unsigned long *ext_tag;
unsigned long post_word;
unsigned long tag, post_word;
char *s;
log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
ext_tag = (unsigned long *)(log_buf)-4;
ext_log_start = (unsigned long *)(log_buf)-3;
ext_log_size = (unsigned long *)(log_buf)-2;
ext_logged_chars = (unsigned long *)(log_buf)-1;
log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
/* Set up log version */
if ((s = getenv ("logversion")) != NULL)
log_version = (int)simple_strtoul (s, NULL, 10);
if (log_version == 2)
tag = log->v2.tag;
else
tag = log->v1.tag;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
if (post_word_load () & POST_COLDBOOT) {
logged_chars = log_size = log_start = 0;
*ext_tag = LOGBUFF_MAGIC;
}
if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
logbuff_reset ();
}
#else
/* No post routines, so we do our own checking */
if (post_word != LOGBUFF_MAGIC) {
logged_chars = log_size = log_start = 0;
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
logbuff_reset ();
post_word_store (LOGBUFF_MAGIC);
*ext_tag = LOGBUFF_MAGIC;
}
}
#endif
if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
log->v2.start = log->v2.con;
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
@ -106,6 +101,15 @@ void logbuff_init_ptrs (void)
gd->post_log_word |= LOGBUFF_INITIALIZED;
}
void logbuff_reset (void)
{
memset (log, 0, sizeof (logbuff_t));
if (log_version == 2)
log->v2.tag = LOGBUFF_MAGIC;
else
log->v1.tag = LOGBUFF_MAGIC;
}
int drv_logbuff_init (void)
{
device_t logdev;
@ -162,7 +166,7 @@ void logbuff_log(char *msg)
int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *s;
unsigned long i;
unsigned long i, start, size;
if (strcmp(argv[1],"append") == 0) {
/* Log concatenation of all arguments separated by spaces */
@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
case 2:
if (strcmp(argv[1],"show") == 0) {
for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
if (log_version == 2) {
start = log->v2.start;
size = log->v2.end - log->v2.start;
}
else {
start = log->v1.start;
size = log->v1.size;
}
for (i=0; i < (size&LOGBUFF_MASK); i++) {
s = (char *)log->buf+((start+i)&LOGBUFF_MASK);
putc (*s);
}
return 0;
} else if (strcmp(argv[1],"reset") == 0) {
log_start = 0;
log_size = 0;
logged_chars = 0;
logbuff_reset ();
return 0;
} else if (strcmp(argv[1],"info") == 0) {
printf ("Logbuffer at %08lx\n", (unsigned long)log_buf);
printf ("log_start = %08lx\n", log_start);
printf ("log_size = %08lx\n", log_size);
printf ("logged_chars = %08lx\n", logged_chars);
printf ("Logbuffer at %08lx\n", (unsigned long)log->buf);
if (log_version == 2) {
printf ("log_start = %08lx\n", log->v2.start);
printf ("log_end = %08lx\n", log->v2.end);
printf ("logged_chars = %08lx\n", log->v2.chars);
}
else {
printf ("log_start = %08lx\n", log->v1.start);
printf ("log_size = %08lx\n", log->v1.size);
printf ("logged_chars = %08lx\n", log->v1.chars);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
}
#if defined(CONFIG_LOGBUFFER)
U_BOOT_CMD(
log, 255, 1, do_log,
"log - manipulate logbuffer\n",
@ -211,7 +228,7 @@ U_BOOT_CMD(
"log show - show contents\n"
"log append <msg> - append <msg> to the logbuffer\n"
);
#endif /* CONFIG_LOGBUFFER */
static int logbuff_printk(const char *line)
{
int i;
@ -241,13 +258,22 @@ static int logbuff_printk(const char *line)
}
line_feed = 0;
for (; p < buf_end; p++) {
log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p;
if (log_size < LOGBUFF_LEN)
log_size++;
else
log_start++;
logged_chars++;
if (log_version == 2) {
log->buf[log->v2.end & LOGBUFF_MASK] = *p;
log->v2.end++;
if (log->v2.end - log->v2.start > LOGBUFF_LEN)
log->v2.start++;
log->v2.chars++;
}
else {
log->buf[(log->v1.start + log->v1.size) &
LOGBUFF_MASK] = *p;
if (log->v1.size < LOGBUFF_LEN)
log->v1.size++;
else
log->v1.start++;
log->v1.chars++;
}
if (*p == '\n') {
line_feed = 1;
break;

38
common/cmd_nand.c
View File

@ -486,17 +486,19 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-56);
return 1;
}
SHOW_BOOT_PROGRESS(56);
hdr = (image_header_t *) addr;
if (ntohl(hdr->ih_magic) != IH_MAGIC) {
printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-57);
return 1;
}
SHOW_BOOT_PROGRESS(57);
print_image_hdr(hdr);
@ -505,9 +507,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
puts("** Read error\n");
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-58);
return 1;
}
SHOW_BOOT_PROGRESS(58);
/* Loading ok, update default load address */
@ -559,6 +562,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
}
#endif
SHOW_BOOT_PROGRESS(52);
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
@ -582,23 +586,26 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
usage:
#endif
printf("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-53);
return 1;
}
SHOW_BOOT_PROGRESS(53);
if (!boot_device) {
puts("\n** No boot device **\n");
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-54);
return 1;
}
SHOW_BOOT_PROGRESS(54);
idx = simple_strtoul(boot_device, NULL, 16);
if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
printf("\n** Device %d not available\n", idx);
SHOW_BOOT_PROGRESS(-1);
SHOW_BOOT_PROGRESS(-55);
return 1;
}
SHOW_BOOT_PROGRESS(55);
return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
}
@ -887,6 +894,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ulong offset = 0;
image_header_t *hdr;
int rcode = 0;
SHOW_BOOT_PROGRESS(52);
switch (argc) {
case 1:
addr = CFG_LOAD_ADDR;
@ -907,24 +915,27 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-53);
return 1;
}
SHOW_BOOT_PROGRESS(53);
if (!boot_device) {
puts ("\n** No boot device **\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-54);
return 1;
}
SHOW_BOOT_PROGRESS(54);
dev = simple_strtoul(boot_device, &ep, 16);
if ((dev >= CFG_MAX_NAND_DEVICE) ||
(nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
printf ("\n** Device %d not available\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-55);
return 1;
}
SHOW_BOOT_PROGRESS(55);
printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
@ -933,9 +944,10 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset,
SECTORSIZE, NULL, (u_char *)addr)) {
printf ("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-56);
return 1;
}
SHOW_BOOT_PROGRESS(56);
hdr = (image_header_t *)addr;
@ -947,17 +959,19 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
cnt -= SECTORSIZE;
} else {
printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic));
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-57);
return 1;
}
SHOW_BOOT_PROGRESS(57);
if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ,
offset + SECTORSIZE, cnt, NULL,
(u_char *)(addr+SECTORSIZE))) {
printf ("** Read error on %d\n", dev);
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-58);
return 1;
}
SHOW_BOOT_PROGRESS(58);
/* Loading ok, update default load address */

26
common/cmd_net.c
View File

@ -30,6 +30,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
extern void show_boot_progress (int val);
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
@ -184,18 +191,25 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
break;
default: printf ("Usage:\n%s\n", cmdtp->usage);
SHOW_BOOT_PROGRESS(-80);
return 1;
}
if ((size = NetLoop(proto)) < 0)
SHOW_BOOT_PROGRESS(80);
if ((size = NetLoop(proto)) < 0) {
SHOW_BOOT_PROGRESS(-81);
return 1;
}
SHOW_BOOT_PROGRESS(81);
/* NetLoop ok, update environment */
netboot_update_env();
/* done if no file was loaded (no errors though) */
if (size == 0)
if (size == 0) {
SHOW_BOOT_PROGRESS(-82);
return 0;
}
/* flush cache */
flush_cache(load_addr, size);
@ -208,14 +222,22 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
printf ("Automatic boot of image at addr 0x%08lX ...\n",
load_addr);
SHOW_BOOT_PROGRESS(82);
rcode = do_bootm (cmdtp, 0, 1, local_args);
}
#ifdef CONFIG_AUTOSCRIPT
if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) {
printf("Running autoscript at addr 0x%08lX ...\n", load_addr);
SHOW_BOOT_PROGRESS(83);
rcode = autoscript (load_addr);
}
#endif
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
if (rcode < 0)
SHOW_BOOT_PROGRESS(-83);
else
SHOW_BOOT_PROGRESS(84);
#endif
return rcode;
}

6
common/cmd_reiser.c
View File

@ -90,7 +90,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
if (!reiserfs_mount(part_length)) {
printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part);
printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part);
return 1;
}
@ -183,7 +183,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
@ -204,7 +204,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
if (!reiserfs_mount(part_length)) {
printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part);
printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part);
return 1;
}

712
common/cmd_sata.c 100644
View File

@ -0,0 +1,712 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to libata in kernel 2.4.32
*
*/
/*
* File contains SATA read-write and other utility functions.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_SATA_SUPPORTED
/*For debug prints set macro DEBUG_SATA to 1 */
#define DEBUG_SATA 0
/*Macro for SATA library specific declarations */
#define SATA_DECL
#include <sata.h>
#undef SATA_DECL
static u8 __inline__
sata_inb (unsigned long ioaddr)
{
return inb (ioaddr);
}
static void __inline__
sata_outb (unsigned char val, unsigned long ioaddr)
{
outb (val, ioaddr);
}
static void
output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
outsw (ioaddr->data_addr, sect_buf, words << 1);
}
static int
input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
insw (ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
static void
sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
last = dst;
end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
goto OUT;
/* skip leading white space */
while ((*src) && (src < end) && (*src == ' '))
++src;
/* copy string, omitting trailing white space */
while ((*src) && (src < end)) {
*dst++ = *src;
if (*src++ != ' ')
last = dst;
}
OUT:
*last = '\0';
}
int
sata_bus_softreset (int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) {
if (!(sata_devchk (&port[num].ioaddr, i))) {
PRINTF ("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
PRINTF ("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
printf ("no devices on port%d\n", num);
return 1;
}
dev_select (&port[num].ioaddr, dev);
port[num].ctl_reg = 0x08; /*Default value of control reg */
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
printf ("ata%u is slow to respond,plz be patient\n", port);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_chk_status (&port[num].ioaddr);
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", port);
printf ("bus reset failed\n");
return 1;
}
return 0;
}
void
sata_identify (int num, int dev)
{
u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
memset (iobuf, 0, sizeof (iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return;
}
printf ("port=%d dev=%d\n", num, dev);
dev_select (&port[num].ioaddr, dev);
status = 0;
cmd = ATA_CMD_IDENT; /*Device Identify Command */
sata_outb (cmd, port[num].ioaddr.command_addr);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
printf ("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
PRINTF ("ata%u: no dma/lba\n", num);
}
ata_dump_id (iobuf);
if (ata_id_has_lba48 (iobuf)) {
n_sectors = ata_id_u64 (iobuf, 100);
} else {
n_sectors = ata_id_u32 (iobuf, 60);
}
PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
sizeof (sata_dev_desc[devno].revision));
sata_cpy (sata_dev_desc[devno].vendor, iop->model,
sizeof (sata_dev_desc[devno].vendor));
sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
sizeof (sata_dev_desc[devno].product));
strswab (sata_dev_desc[devno].revision);
strswab (sata_dev_desc[devno].vendor);
if ((iop->config & 0x0080) == 0x0080) {
sata_dev_desc[devno].removable = 1;
} else {
sata_dev_desc[devno].removable = 0;
}
sata_dev_desc[devno].lba = iop->lba_capacity;
PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lba48 = 1;
lba = (unsigned long long) iop->lba48_capacity[0] |
((unsigned long long) iop->lba48_capacity[1] << 16) |
((unsigned long long) iop->lba48_capacity[2] << 32) |
((unsigned long long) iop->lba48_capacity[3] << 48);
} else {
sata_dev_desc[devno].lba48 = 0;
}
#endif
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
void
set_Feature_cmd (int num, int dev)
{
u8 mask = 0x00, status = 0;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
PRINTF ("dev%d is not present on port#%d\n", dev, num);
return;
}
dev_select (&port[num].ioaddr, dev);
sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
sata_outb (0, port[num].ioaddr.lbal_addr);
sata_outb (0, port[num].ioaddr.lbam_addr);
sata_outb (0, port[num].ioaddr.lbah_addr);
sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
udelay (50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
printf ("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
void
sata_port (struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
int
sata_devchk (struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
dev_select (ioaddr, dev);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
sata_outb (0xaa, ioaddr->nsect_addr);
sata_outb (0x55, ioaddr->lbal_addr);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
nsect = sata_inb (ioaddr->nsect_addr);
lbal = sata_inb (ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
else
return 0; /* nothing found */
}
void
dev_select (struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
if (dev == 0)
tmp = ATA_DEVICE_OBS;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
sata_outb (tmp, ioaddr->device_addr);
sata_inb (ioaddr->altstatus_addr);
udelay (5);
}
u8
sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
udelay (1000);
status = sata_chk_status (ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
u8
sata_chk_status (struct sata_ioports * ioaddr)
{
return sata_inb (ioaddr->status_addr);
}
void
msleep (int count)
{
int i;
for (i = 0; i < count; i++)
udelay (1000);
}
ulong
sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb (((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
err = sata_inb (port[num].ioaddr.error_addr);
printf ("Error reg = 0x%x\n", err);
return (n);
}
input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
ulong
sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the Port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
return (n);
}
output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
block_dev_desc_t *sata_get_dev (int dev);
block_dev_desc_t *
sata_get_dev (int dev)
{
return ((block_dev_desc_t *) & sata_dev_desc[dev]);
}
int
do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
switch (argc) {
case 0:
case 1:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strncmp (argv[1], "init", 4) == 0) {
int rcode = 0;
rcode = init_sata ();
if (rcode)
printf ("Sata initialization Failed\n");
return rcode;
} else if (strncmp (argv[1], "inf", 3) == 0) {
int i;
putc ('\n');
for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) {
/*List only known devices */
if (sata_dev_desc[i].type ==
DEV_TYPE_UNKNOWN)
continue;
printf ("sata dev %d: ", i);
dev_print (&sata_dev_desc[i]);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 3:
if (strcmp (argv[1], "dev") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
printf ("\nSATA dev %d: ", dev);
dev_print (&sata_dev_desc[dev]);
if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
return 1;
curr_dev = dev;
return 0;
} else if (strcmp (argv[1], "part") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
PRINTF ("\nSATA dev %d: ", dev);
if (sata_dev_desc[dev].part_type !=
PART_TYPE_UNKNOWN) {
print_part (&sata_dev_desc[dev]);
} else {
printf ("\nSata dev %d partition type "
"unknown\n", dev);
return 1;
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
default:
if (argc < 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp (argv[1], "read") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
memset ((int *) addr, 0, cnt * 512);
printf ("\nSATA read: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_read (curr_dev, blk, cnt, (ulong *) addr);
/* flush cache after read */
flush_cache (addr, cnt * 512);
printf ("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else if (strcmp (argv[1], "write") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
printf ("\nSata write: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_write (curr_dev, blk, cnt, (ulong *) addr);
printf ("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
} /*End OF SWITCH */
}
U_BOOT_CMD (sata, 5, 1, do_sata,
"sata init\n"
"sata info\n"
"sata part device\n"
"sata dev device\n"
"sata read addr blk# cnt\n"
"sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n");
#endif

2
common/env_common.c
View File

@ -232,7 +232,7 @@ void env_relocate (void)
puts ("Using default environment\n\n");
#else
puts ("*** Warning - bad CRC, using default environment\n\n");
SHOW_BOOT_PROGRESS (-1);
SHOW_BOOT_PROGRESS (-60);
#endif
if (sizeof(default_environment) > ENV_SIZE)

12
common/main.c
View File

@ -113,7 +113,7 @@ static __inline__ int abortboot(int bootdelay)
u_int i;
# ifdef CONFIG_AUTOBOOT_PROMPT
printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
# endif
# ifdef CONFIG_AUTOBOOT_DELAY_STR
@ -187,7 +187,7 @@ static __inline__ int abortboot(int bootdelay)
}
# if DEBUG_BOOTKEYS
if (!abort)
puts ("key timeout\n");
puts("key timeout\n");
# endif
#ifdef CONFIG_SILENT_CONSOLE
@ -244,13 +244,13 @@ static __inline__ int abortboot(int bootdelay)
# endif
break;
}
udelay (10000);
udelay(10000);
}
printf ("\b\b\b%2d ", bootdelay);
printf("\b\b\b%2d ", bootdelay);
}
putc ('\n');
putc('\n');
#ifdef CONFIG_SILENT_CONSOLE
if (abort)
@ -962,7 +962,7 @@ int readline (const char *const prompt)
n = 0;
continue;
case 0x17: /* ^W - erase word */
case 0x17: /* ^W - erase word */
p=delete_char(console_buffer, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
p=delete_char(console_buffer, p, &col, &n, plen);

4
cpu/74xx_7xx/start.S
View File

@ -125,7 +125,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -143,7 +143,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

2
cpu/i386/start.S
View File

@ -149,7 +149,7 @@ data_ok:
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
movl $_i386boot_bss_start, %eax /* BSS start */
movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */
movl $_i386boot_bss_size, %ecx /* BSS size */
movl %ecx, %eax
andl $3, %eax

6
cpu/mpc5xx/start.S
View File

@ -155,7 +155,7 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */
@ -210,7 +210,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -228,7 +228,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc5xxx/start.S
View File

@ -208,7 +208,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -227,7 +227,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc8220/start.S
View File

@ -169,7 +169,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -188,7 +188,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc824x/start.S
View File

@ -220,7 +220,7 @@ _start_of_vectors:
/* Alignment exception. */
. = EXC_OFF_ALIGN
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -238,7 +238,7 @@ Alignment:
/* Program check exception */
. = EXC_OFF_PROGRAM
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

8
cpu/mpc8260/start.S
View File

@ -279,7 +279,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -298,7 +298,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
@ -676,13 +676,13 @@ init_debug:
bdnz 1b
/* Load the Instruction Address Breakpoint Register (IABR). */
/* */
/* */
/* The address to load is stored in the first word of dual port */
/* ram and should be preserved while the power is on, so you */
/* can plug addresses into that location then reset the cpu and */
/* this code will load that address into the IABR after the */
/* reset. */
/* */
/* */
/* When the program counter matches the contents of the IABR, */
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */

8
cpu/mpc83xx/cpu.c
View File

@ -415,7 +415,7 @@ static const struct {
"clock-frequency",
fdt_set_busfreq
},
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
{ "/" OF_SOC "/ethernet@24000,
"mac-address",
fdt_set_eth0
@ -425,7 +425,7 @@ static const struct {
fdt_set_eth0
},
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
{ "/" OF_SOC "/ethernet@25000,
"mac-address",
fdt_set_eth1
@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);

4
cpu/mpc83xx/start.S
View File

@ -263,7 +263,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -282,7 +282,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

2
cpu/mpc85xx/cpu.c
View File

@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC85XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);

4
cpu/mpc85xx/start.S
View File

@ -457,7 +457,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x0600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -475,7 +475,7 @@ Alignment:
/* Program check exception */
. = 0x0700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

8
cpu/mpc86xx/cpu.c
View File

@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC86XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
#if defined(CONFIG_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC3)
#if defined(CONFIG_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6);
@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC4)
#if defined(CONFIG_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6);

4
cpu/mpc86xx/start.S
View File

@ -116,7 +116,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -134,7 +134,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc8xx/start.S
View File

@ -224,7 +224,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -242,7 +242,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

30
cpu/ppc4xx/405gp_pci.c
View File

@ -77,11 +77,21 @@
#include <asm/processor.h>
#include <pci.h>
#ifdef CONFIG_PCI
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
*/
int __pci_pre_init(struct pci_controller *hose)
{
return 1;
}
int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
#ifdef CONFIG_PCI
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
@ -191,6 +201,13 @@ void pci_405gp_init(struct pci_controller *hose)
if (hose->pci_fb)
pciauto_region_init(hose->pci_fb);
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
pci_register_hose(hose);
/*--------------------------------------------------------------------------+
@ -416,14 +433,12 @@ void pci_init_board(void)
#endif
#endif /* CONFIG_PCI */
#endif /* CONFIG_405GP */
/*-----------------------------------------------------------------------------+
* CONFIG_440
*-----------------------------------------------------------------------------*/
#if defined(CONFIG_440) && defined(CONFIG_PCI)
#if defined(CONFIG_440)
static struct pci_controller ppc440_hose = {0};
@ -496,14 +511,12 @@ void pci_440_init (struct pci_controller *hose)
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
pci_register_hose( hose );
@ -575,4 +588,5 @@ void pci_init_board(void)
#endif
}
#endif /* CONFIG_440 & CONFIG_PCI */
#endif /* CONFIG_440 */
#endif /* CONFIG_PCI */

36
cpu/ppc4xx/44x_spd_ddr.c
View File

@ -70,6 +70,15 @@
#define ONE_BILLION 1000000000
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
*/
void __spd_ddr_init_hang (void)
{
hang ();
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
@ -262,7 +271,7 @@ typedef struct bank_param BANKPARMS;
#ifdef CFG_SIMULATE_SPD_EEPROM
extern unsigned char cfg_simulate_spd_eeprom[128];
#endif
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static unsigned char spd_read(uchar chip, uint addr);
static void get_spd_info(unsigned long *dimm_populated,
@ -373,7 +382,7 @@ long int spd_sdram(void) {
#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
/* and program tlb entries for this size (dynamic) */
program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
#endif
/*
@ -467,7 +476,7 @@ static void get_spd_info(unsigned long *dimm_populated,
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@ -490,7 +499,7 @@ static void check_mem_type(unsigned long *dimm_populated,
dimm_num);
printf("Only DDR SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
}
@ -510,7 +519,7 @@ static void check_volt_type(unsigned long *dimm_populated,
if (voltage_type != 0x04) {
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
dimm_num);
hang();
spd_ddr_init_hang ();
} else {
debug("DIMM %lu voltage level supported.\n", dimm_num);
}
@ -581,7 +590,7 @@ static void program_cfg0(unsigned long *dimm_populated,
printf("WARNING: DIMM with datawidth of %lu bits.\n",
data_width);
printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
hang();
spd_ddr_init_hang ();
}
break;
}
@ -769,7 +778,7 @@ static void program_tr0(unsigned long *dimm_populated,
if ((tcyc_reg & 0x0F) >= 10) {
printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
dimm_num);
hang();
spd_ddr_init_hang ();
}
cycle_time_ns_x_10[cas_index] =
@ -849,7 +858,7 @@ static void program_tr0(unsigned long *dimm_populated,
printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range.\n");
hang();
spd_ddr_init_hang ();
}
/*
@ -1008,6 +1017,7 @@ static int short_mem_test(void)
*/
for (i = 0; i < NUMMEMTESTS; i++) {
for (j = 0; j < NUMMEMWORDS; j++) {
//printf("bank enabled base:%x\n", &membase[j]);
membase[j] = test[i][j];
ppcDcbf((unsigned long)&(membase[j]));
}
@ -1160,7 +1170,7 @@ static void program_tr1(void)
*/
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay.\n");
hang();
spd_ddr_init_hang ();
}
/*
@ -1310,7 +1320,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for the banksize: %d.\n",
bank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
switch (num_col_addr) {
@ -1332,7 +1342,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
/*
@ -1340,14 +1350,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
for (i = 0; i < num_banks; i++) {
for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
}
}
}
}

82
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -58,8 +58,8 @@
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
@ -129,6 +129,16 @@
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
/*
* Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
*/
void __spd_ddr_init_hang (void)
{
hang ();
}
void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
/* Private Structure Definitions */
/* enum only to ease code for cas latency setting */
@ -144,7 +154,7 @@ typedef enum ddr_cas_id {
* Prototypes
*-----------------------------------------------------------------------------*/
static unsigned long sdram_memsize(void);
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
@ -528,7 +538,7 @@ long int initdram(int board_type)
dram_size = sdram_memsize();
/* and program tlb entries for this size (dynamic) */
program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
/*------------------------------------------------------------------
* DQS calibration.
@ -582,7 +592,7 @@ static void get_spd_info(unsigned long *dimm_populated,
if (dimm_found == FALSE) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@ -629,42 +639,42 @@ static void check_mem_type(unsigned long *dimm_populated,
"slot %d.\n", (unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 2:
printf("ERROR: EDO DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 3:
printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 4:
printf("ERROR: SDRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 5:
printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 6:
printf("ERROR: SGRAM DIMM detected in slot %d.\n",
(unsigned int)dimm_num);
printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
case 7:
debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
@ -679,7 +689,7 @@ static void check_mem_type(unsigned long *dimm_populated,
(unsigned int)dimm_num);
printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
}
@ -689,7 +699,7 @@ static void check_mem_type(unsigned long *dimm_populated,
&& (dimm_populated[dimm_num] != SDRAM_NONE)
&& (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
hang();
spd_ddr_init_hang ();
}
}
}
@ -764,7 +774,7 @@ static void check_frequency(unsigned long *dimm_populated,
(unsigned int)(calc_cycle_time*10));
printf("Replace the DIMM, or change DDR frequency via "
"strapping bits.\n\n");
hang();
spd_ddr_init_hang ();
}
}
}
@ -796,7 +806,7 @@ static void check_rank_number(unsigned long *dimm_populated,
"slot %d is not supported.\n", dimm_rank, dimm_num);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
} else
total_rank += dimm_rank;
}
@ -805,7 +815,7 @@ static void check_rank_number(unsigned long *dimm_populated,
"for all slots.\n", (unsigned int)total_rank);
printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
printf("Remove one of the DIMM modules.\n\n");
hang();
spd_ddr_init_hang ();
}
}
}
@ -830,28 +840,28 @@ static void check_voltage_type(unsigned long *dimm_populated,
printf("This DIMM is 5.0 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x01:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is LVTTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x02:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 1.5 Volt.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x03:
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("This DIMM is 3.3 Volt/TTL.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
case 0x04:
/* 2.5 Voltage only for DDR1 */
@ -863,7 +873,7 @@ static void check_voltage_type(unsigned long *dimm_populated,
printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
(unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
break;
}
}
@ -1006,13 +1016,13 @@ static void program_copt1(unsigned long *dimm_populated,
if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
if (buf0 != buf1) {
printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
hang();
spd_ddr_init_hang ();
}
}
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
hang();
spd_ddr_init_hang ();
}
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
@ -1020,7 +1030,7 @@ static void program_copt1(unsigned long *dimm_populated,
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
hang();
spd_ddr_init_hang ();
}
if (ecc_enabled == TRUE)
@ -1209,7 +1219,7 @@ static void program_initplr(unsigned long *dimm_populated,
break;
default:
printf("ERROR: ucode error on selected_cas value %d", selected_cas);
hang();
spd_ddr_init_hang ();
break;
}
@ -1241,7 +1251,7 @@ static void program_initplr(unsigned long *dimm_populated,
break;
default:
printf("ERROR: write recovery not support (%d)", write_recovery);
hang();
spd_ddr_init_hang ();
break;
}
#else
@ -1259,7 +1269,7 @@ static void program_initplr(unsigned long *dimm_populated,
ods = ODS_REDUCED;
} else {
printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
hang();
spd_ddr_init_hang ();
}
mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
@ -1284,7 +1294,7 @@ static void program_initplr(unsigned long *dimm_populated,
mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
} else {
printf("ERROR: ucode error as unknown DDR type in program_initplr");
hang();
spd_ddr_init_hang ();
}
}
@ -1389,7 +1399,7 @@ static void program_mode(unsigned long *dimm_populated,
} else {
printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
"in slot %d\n", (unsigned int)dimm_num);
hang();
spd_ddr_init_hang ();
}
} else {
/* Convert from hex to decimal */
@ -1526,7 +1536,7 @@ static void program_mode(unsigned long *dimm_populated,
printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
hang();
spd_ddr_init_hang ();
}
} else { /* DDR2 */
debug("cas_3_0_available=%d\n", cas_3_0_available);
@ -1549,7 +1559,7 @@ static void program_mode(unsigned long *dimm_populated,
cas_3_0_available, cas_4_0_available, cas_5_0_available);
printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
hang();
spd_ddr_init_hang ();
}
}
@ -1658,7 +1668,7 @@ static void program_rtr(unsigned long *dimm_populated,
printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
(unsigned int)dimm_num);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
break;
}
@ -2066,7 +2076,7 @@ static void program_bxcf(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for number of "
"column addresses: %d.\n", (unsigned int)num_col_addr);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
}
@ -2148,7 +2158,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
printf("ERROR: Unsupported value for the banksize: %d.\n",
(unsigned int)rank_size_id);
printf("Replace the DIMM module with a supported DIMM.\n\n");
hang();
spd_ddr_init_hang ();
}
if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
@ -2693,7 +2703,7 @@ calibration_loop:
printf("\nERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
hang();
spd_ddr_init_hang ();
}
blank_string(strlen(str));
@ -2849,7 +2859,7 @@ static void test(void)
if (window_found == FALSE) {
printf("ERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
hang();
spd_ddr_init_hang ();
}
/*------------------------------------------------------------------

10
cpu/ppc4xx/config.mk
View File

@ -22,5 +22,13 @@
#
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float
PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
ifneq (,$(findstring CONFIG_440,$(is440)))
PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
else
PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
endif

4
cpu/ppc4xx/cpu_init.c
View File

@ -153,7 +153,7 @@ cpu_init_f (void)
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
@ -211,6 +211,8 @@ cpu_init_f (void)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
val |= 0xb0000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif

42
cpu/ppc4xx/gpio.c
View File

@ -103,6 +103,18 @@ void gpio_write_bit(int pin, int val)
out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
}
int gpio_read_out_bit(int pin)
{
u32 offs = 0;
if (pin >= GPIO_MAX) {
offs = 0x100;
pin -= GPIO_MAX;
}
return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
}
#if defined(CFG_440_GPIO_TABLE)
void gpio_set_chip_configuration(void)
{
@ -157,12 +169,38 @@ void gpio_set_chip_configuration(void)
switch (gpio_tab[gpio_core][i].alt_nb) {
case GPIO_SEL:
if (gpio_core == GPIO0) {
reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
/*
* Setup output value
* 1 -> high level
* 0 -> low level
* else -> don't touch
*/
reg = in32(GPIO0_OR);
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
reg |= (0x80000000 >> (i));
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
reg &= ~(0x80000000 >> (i));
out32(GPIO0_OR, reg);
reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
out32(GPIO0_TCR, reg);
}
if (gpio_core == GPIO1) {
reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
/*
* Setup output value
* 1 -> high level
* 0 -> low level
* else -> don't touch
*/
reg = in32(GPIO0_OR);
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
reg |= (0x80000000 >> (i));
else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
reg &= ~(0x80000000 >> (i));
out32(GPIO0_OR, reg);
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
out32(GPIO1_TCR, reg);
}

447
cpu/ppc4xx/start.S
View File

@ -22,26 +22,27 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*------------------------------------------------------------------------------+ */
/* */
/* This source code has been made available to you by IBM on an AS-IS */
/* basis. Anyone receiving this source is licensed under IBM */
/* copyrights to use it in any way he or she deems fit, including */
/* copying it, modifying it, compiling it, and redistributing it either */
/* with or without modifications. No license under IBM patents or */
/* patent applications is to be implied by the copyright license. */
/* */
/* Any user of this software should understand that IBM cannot provide */
/* technical support for this software and will not be responsible for */
/* any consequences resulting from the use of this software. */
/* */
/* Any person who transfers this source code or any derivative work */
/* must include the IBM copyright notice, this paragraph, and the */
/* preceding two paragraphs in the transferred software. */
/* */
/* COPYRIGHT I B M CORPORATION 1995 */
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */
/*------------------------------------------------------------------------------+
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*-------------------------------------------------------------------------------
*/
/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
*
@ -59,7 +60,6 @@
* address and (s)dram will be positioned at address 0
*/
#include <config.h>
#include <mpc8xx.h>
#include <ppc4xx.h>
#include <version.h>
@ -110,11 +110,11 @@
# endif
#endif /* CFG_INIT_DCACHE_CS */
#define function_prolog(func_name) .text; \
#define function_prolog(func_name) .text; \
.align 2; \
.globl func_name; \
func_name:
#define function_epilog(func_name) .type func_name,@function; \
#define function_epilog(func_name) .type func_name,@function; \
.size func_name,.-func_name
/* We don't want the MMU yet.
@ -294,11 +294,13 @@ skip_debug_init:
mtspr ivor7,r1 /* Floating point unavailable */
li r1,0x0c00
mtspr ivor8,r1 /* System call */
li r1,0x1000
mtspr ivor10,r1 /* Decrementer (PIT for 440) */
li r1,0x1400
mtspr ivor13,r1 /* Data TLB error */
li r1,0x0a00
mtspr ivor9,r1 /* Auxiliary Processor unavailable */
li r1,0x0900
mtspr ivor10,r1 /* Decrementer */
li r1,0x1300
mtspr ivor13,r1 /* Data TLB error */
li r1,0x1400
mtspr ivor14,r1 /* Instr TLB error */
li r1,0x2000
mtspr ivor15,r1 /* Debug */
@ -503,11 +505,81 @@ version_string:
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"
/*
* Maybe this should be moved somewhere else because the current
* location (0x100) is where the CriticalInput Execption should be.
*/
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
/* Critical input. */
CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
#ifdef CONFIG_440
/* Machine check */
MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
#else
CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
#endif /* CONFIG_440 */
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_Alignment:
.long AlignmentException - _start + _START_OFFSET
.long int_return - _start + _START_OFFSET
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_ProgramCheck:
.long ProgramCheckException - _start + _START_OFFSET
.long int_return - _start + _START_OFFSET
#ifdef CONFIG_440
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
STD_EXCEPTION(0xa00, APU, UnknownException)
#endif
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
#ifdef CONFIG_440
STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
#else
STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
#endif
CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
.globl _end_of_vectors
_end_of_vectors:
. = _START_OFFSET
#endif
.globl _start
_start:
@ -817,21 +889,21 @@ _start:
*/
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CFG_OCM_DATA_ADDR@l
ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmplb3cr1,r3 /* Set PLB Access */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
mtdcr ocmplb3cr2,r3 /* Set PLB Access */
isync
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CFG_OCM_DATA_ADDR@l
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmdscr1, r3 /* Set Data Side */
mtdcr ocmiscr1, r3 /* Set Instruction Side */
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmdscr1, r3 /* Set Data Side */
mtdcr ocmiscr1, r3 /* Set Instruction Side */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
mtdcr ocmdscr2, r3 /* Set Data Side */
mtdcr ocmiscr2, r3 /* Set Instruction Side */
addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
mtdcr ocmdscr2, r3 /* Set Data Side */
mtdcr ocmiscr2, r3 /* Set Instruction Side */
addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
mtdcr ocmdsisdpc,r3
isync
@ -850,7 +922,7 @@ _start:
mtdcr ocmdscntl, r4 /* set data-side IRAM config */
isync
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CFG_OCM_DATA_ADDR@l
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
@ -1017,107 +1089,6 @@ start_ram:
#ifndef CONFIG_NAND_SPL
/*****************************************************************************/
.globl _start_of_vectors
_start_of_vectors:
#if 0
/*TODO Fixup _start above so we can do this*/
/* Critical input. */
CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
#endif
/* Machine check */
CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_Alignment:
.long AlignmentException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
lwz r6,GOT(transfer_to_handler)
mtlr r6
blrl
.L_ProgramCheck:
.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
.long int_return - _start + EXC_OFF_SYS_RESET
/* No FPU on MPC8xx. This exception is not supposed to happen.
*/
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
/* On the MPC8xx, this is a software emulation interrupt. It occurs
* for all unimplemented and illegal instructions.
*/
STD_EXCEPTION(0x1000, PIT, PITException)
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
STD_EXCEPTION(0x1500, Reserved5, UnknownException)
STD_EXCEPTION(0x1600, Reserved6, UnknownException)
STD_EXCEPTION(0x1700, Reserved7, UnknownException)
STD_EXCEPTION(0x1800, Reserved8, UnknownException)
STD_EXCEPTION(0x1900, Reserved9, UnknownException)
STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
.globl _end_of_vectors
_end_of_vectors:
. = 0x2100
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
@ -1133,28 +1104,12 @@ transfer_to_handler:
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
#if 0
andi. r23,r23,MSR_PR
mfspr r23,SPRG3 /* if from user, fix up tss.regs */
beq 2f
addi r24,r1,STACK_FRAME_OVERHEAD
stw r24,PT_REGS(r23)
2: addi r2,r23,-TSS /* set r2 to current */
tovirt(r2,r2,r23)
#endif
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
mtspr SPRG2,r22 /* r1 is now kernel sp */
#if 0
addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
cmplw 0,r1,r2
cmplw 1,r1,r24
crand 1,1,4
bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
#endif
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
@ -1215,16 +1170,72 @@ crit_return:
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr 990,r2 /* SRR2 */
mtspr 991,r0 /* SRR3 */
mtspr csrr0,r2
mtspr csrr1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfci
/* Cache functions.
*/
#ifdef CONFIG_440
mck_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr mcsrr0,r2
mtspr mcsrr1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfmci
#endif /* CONFIG_440 */
/*
* Cache functions.
*
* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
* although for some cache-ralated calls stubs have to be provided to satisfy
* symbols resolution.
* Icache-related functions are used in POST framework.
*
*/
#ifdef CONFIG_440
.globl dcache_disable
.globl icache_disable
.globl icache_enable
dcache_disable:
icache_disable:
icache_enable:
blr
.globl dcache_status
.globl icache_status
dcache_status:
icache_status:
mr r3, 0
blr
#else
flush_dcache:
addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
ori r9,r9,0x8000
@ -1303,24 +1314,13 @@ dcache_status:
mfdccr r3
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
#endif
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
#if !defined(CONFIG_440)
.globl wr_pit
wr_pit:
mtspr pit, r3
blr
#endif
.globl wr_tcr
wr_tcr:
mtspr tcr, r3
blr
/*------------------------------------------------------------------------------- */
/* Function: out16 */
/* Description: Output 16 bits */
@ -1518,7 +1518,7 @@ relocate_code:
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
addi r0, r10, in_ram - _start + _START_OFFSET
mtlr r0
blr /* NEVER RETURNS! */
@ -1588,7 +1588,7 @@ clear_bss:
*/
.globl trap_init
trap_init:
lwz r7, GOT(_start)
lwz r7, GOT(_start_of_vectors)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector always at 0x100 */
@ -1608,35 +1608,48 @@ trap_init:
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
li r7, .L_MachineCheck - _start + _START_OFFSET
li r8, Alignment - _start + _START_OFFSET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
li r7, .L_Alignment - _start + _START_OFFSET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
li r7, .L_ProgramCheck - _start + _START_OFFSET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
#ifdef CONFIG_440
li r7, .L_FPUnavailable - _start + _START_OFFSET
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
li r7, .L_Decrementer - _start + _START_OFFSET
bl trap_reloc
li r7, .L_APU - _start + _START_OFFSET
bl trap_reloc
li r7, .L_InstructionTLBError - _start + _START_OFFSET
bl trap_reloc
li r7, .L_DataTLBError - _start + _START_OFFSET
bl trap_reloc
#else /* CONFIG_440 */
li r7, .L_PIT - _start + _START_OFFSET
bl trap_reloc
li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
bl trap_reloc
li r7, .L_DataTLBMiss - _start + _START_OFFSET
bl trap_reloc
#endif /* CONFIG_440 */
li r7, .L_DebugBreakpoint - _start + _START_OFFSET
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
#if !defined(CONFIG_440)
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
@ -1679,13 +1692,13 @@ trap_reloc:
+----------------------------------------------------------------------------*/
function_prolog(dcbz_area)
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ra2
addi r5,r5,0x0001
..d_ra2:mtctr r5
..d_ag2:dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag2
rlwinm r5,r4,27,5,31
beq ..d_ra2
addi r5,r5,0x0001
..d_ra2:mtctr r5
..d_ag2:dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag2
sync
blr
function_epilog(dcbz_area)
@ -1694,26 +1707,26 @@ trap_reloc:
| dflush. Assume 32K at vector address is cachable.
+----------------------------------------------------------------------------*/
function_prolog(dflush)
mfmsr r9
rlwinm r8,r9,0,15,13
rlwinm r8,r8,0,17,15
mtmsr r8
addi r3,r0,0x0000
mtspr dvlim,r3
mfspr r3,ivpr
addi r4,r0,1024
mtctr r4
mfmsr r9
rlwinm r8,r9,0,15,13
rlwinm r8,r8,0,17,15
mtmsr r8
addi r3,r0,0x0000
mtspr dvlim,r3
mfspr r3,ivpr
addi r4,r0,1024
mtctr r4
..dflush_loop:
lwz r6,0x0(r3)
addi r3,r3,32
bdnz ..dflush_loop
addi r3,r3,-32
mtctr r4
..ag: dcbf r0,r3
addi r3,r3,-32
bdnz ..ag
lwz r6,0x0(r3)
addi r3,r3,32
bdnz ..dflush_loop
addi r3,r3,-32
mtctr r4
..ag: dcbf r0,r3
addi r3,r3,-32
bdnz ..ag
sync
mtmsr r9
mtmsr r9
blr
function_epilog(dflush)
#endif /* CONFIG_440 */

85
cpu/ppc4xx/tlb.c
View File

@ -36,7 +36,8 @@ typedef struct region {
unsigned long tlb_word2_i_value;
} region_t;
static int add_tlb_entry(unsigned long base_addr,
static int add_tlb_entry(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long tlb_word0_size_value,
unsigned long tlb_word2_i_value)
{
@ -55,9 +56,9 @@ static int add_tlb_entry(unsigned long base_addr,
return -1;
/* Second, create the TLB entry */
tlb_word0_value = TLB_WORD0_EPN_ENCODE(base_addr) | TLB_WORD0_V_ENABLE |
tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
TLB_WORD0_TS_0 | tlb_word0_size_value;
tlb_word1_value = TLB_WORD1_RPN_ENCODE(base_addr) | TLB_WORD1_ERPN_ENCODE(0);
tlb_word1_value = TLB_WORD1_RPN_ENCODE(phys_addr) | TLB_WORD1_ERPN_ENCODE(0);
tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
TLB_WORD2_W_DISABLE | tlb_word2_i_value |
@ -81,7 +82,9 @@ static int add_tlb_entry(unsigned long base_addr,
return 0;
}
static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
static void program_tlb_addr(unsigned long phys_addr,
unsigned long virt_addr,
unsigned long mem_size,
unsigned long tlb_word2_i_value)
{
int rc;
@ -91,70 +94,86 @@ static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
while (mem_size != 0) {
rc = 0;
/* Add the TLB entries in to map the region. */
if (((base_addr & TLB_256MB_ALIGN_MASK) == base_addr) &&
if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_256MB_SIZE)) {
/* Add a 256MB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
mem_size -= TLB_256MB_SIZE;
base_addr += TLB_256MB_SIZE;
phys_addr += TLB_256MB_SIZE;
virt_addr += TLB_256MB_SIZE;
}
} else if (((base_addr & TLB_16MB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_16MB_SIZE)) {
/* Add a 16MB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
mem_size -= TLB_16MB_SIZE;
base_addr += TLB_16MB_SIZE;
phys_addr += TLB_16MB_SIZE;
virt_addr += TLB_16MB_SIZE;
}
} else if (((base_addr & TLB_1MB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_1MB_SIZE)) {
/* Add a 1MB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
mem_size -= TLB_1MB_SIZE;
base_addr += TLB_1MB_SIZE;
phys_addr += TLB_1MB_SIZE;
virt_addr += TLB_1MB_SIZE;
}
} else if (((base_addr & TLB_256KB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_256KB_SIZE)) {
/* Add a 256KB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
mem_size -= TLB_256KB_SIZE;
base_addr += TLB_256KB_SIZE;
phys_addr += TLB_256KB_SIZE;
virt_addr += TLB_256KB_SIZE;
}
} else if (((base_addr & TLB_64KB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_64KB_SIZE)) {
/* Add a 64KB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
mem_size -= TLB_64KB_SIZE;
base_addr += TLB_64KB_SIZE;
phys_addr += TLB_64KB_SIZE;
virt_addr += TLB_64KB_SIZE;
}
} else if (((base_addr & TLB_16KB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_16KB_SIZE)) {
/* Add a 16KB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
mem_size -= TLB_16KB_SIZE;
base_addr += TLB_16KB_SIZE;
phys_addr += TLB_16KB_SIZE;
virt_addr += TLB_16KB_SIZE;
}
} else if (((base_addr & TLB_4KB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_4KB_SIZE)) {
/* Add a 4KB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
mem_size -= TLB_4KB_SIZE;
base_addr += TLB_4KB_SIZE;
phys_addr += TLB_4KB_SIZE;
virt_addr += TLB_4KB_SIZE;
}
} else if (((base_addr & TLB_1KB_ALIGN_MASK) == base_addr) &&
} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_1KB_SIZE)) {
/* Add a 1KB TLB entry */
if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
if ((rc = add_tlb_entry(phys_addr, virt_addr,
TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
mem_size -= TLB_1KB_SIZE;
base_addr += TLB_1KB_SIZE;
phys_addr += TLB_1KB_SIZE;
virt_addr += TLB_1KB_SIZE;
}
} else {
printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
base_addr);
phys_addr);
}
if (rc != 0)
printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
base_addr);
phys_addr);
}
return;
@ -166,16 +185,16 @@ static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
* Common usage for boards with SDRAM DIMM modules to dynamically
* configure the TLB's for the SDRAM
*/
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value)
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
{
region_t region_array;
region_array.base = start;
region_array.base = phys_addr;
region_array.size = size;
region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
/* Call the routine to add in the tlb entries for the memory regions */
program_tlb_addr(region_array.base, region_array.size,
program_tlb_addr(region_array.base, virt_addr, region_array.size,
region_array.tlb_word2_i_value);
return;

176
cpu/ppc4xx/traps.c 100644 → 100755
View File

@ -36,6 +36,8 @@
#include <command.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
@ -45,8 +47,7 @@ extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
#define END_OF_MEM 0x00400000
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
static __inline__ void set_tsr(unsigned long val)
{
@ -110,7 +111,7 @@ void show_regs(struct pt_regs * regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
@ -120,14 +121,12 @@ void show_regs(struct pt_regs * regs)
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
if ((i % 8) == 0) {
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
if ((i % 8) == 7) {
printf("\n");
}
}
@ -139,13 +138,16 @@ _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
panic("Exception");
}
void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
u32 value2;
#endif
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
@ -161,26 +163,132 @@ MachineCheckException(struct pt_regs *regs)
return;
#endif
printf("Machine check in kernel mode.\n");
printf("Machine Check Exception.\n");
printf("Caused by (from msr): ");
printf("regs %p ",regs);
switch( regs->msr & 0x000F0000) {
case (0x80000000>>12):
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
printf("regs %p ", regs);
val = get_esr();
#if !defined(CONFIG_440)
if (val& ESR_IMCP) {
printf("Instruction");
mtspr(ESR, val & ~ESR_IMCP);
} else {
printf("Data");
}
printf(" machine check.\n");
#elif defined(CONFIG_440)
if (val& ESR_IMCP){
printf("Instruction Synchronous Machine Check exception\n");
mtspr(SPRN_ESR, val & ~ESR_IMCP);
} else {
val = mfspr(MCSR);
if (val & MCSR_IB)
printf("Instruction Read PLB Error\n");
if (val & MCSR_DRB)
printf("Data Read PLB Error\n");
if (val & MCSR_DWB)
printf("Data Write PLB Error\n");
if (val & MCSR_TLBP)
printf("TLB Parity Error\n");
if (val & MCSR_ICP){
/*flush_instruction_cache(); */
printf("I-Cache Parity Error\n");
}
if (val & MCSR_DCSP)
printf("D-Cache Search Parity Error\n");
if (val & MCSR_DCFP)
printf("D-Cache Flush Parity Error\n");
if (val & MCSR_IMPE)
printf("Machine Check exception is imprecise\n");
/* Clear MCSR */
mtspr(SPRN_MCSR, val);
}
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
printf("DDR0: DDR0_00 %p\n", val);
val = (val >> 16) & 0xff;
if (val & 0x80)
printf("DDR0: At least one interrupt active\n");
if (val & 0x40)
printf("DDR0: DRAM initialization complete.\n");
if (val & 0x20)
printf("DDR0: Multiple uncorrectable ECC events.\n");
if (val & 0x10)
printf("DDR0: Single uncorrectable ECC event.\n");
if (val & 0x08)
printf("DDR0: Multiple correctable ECC events.\n");
if (val & 0x04)
printf("DDR0: Single correctable ECC event.\n");
if (val & 0x02)
printf("Multiple accesses outside the defined"
" physical memory space detected\n");
if (val & 0x01)
printf("DDR0: Single access outside the defined"
" physical memory space detected.\n");
mfsdram(DDR0_01, val);
val = (val >> 8) & 0x7;
switch (val ) {
case 0:
printf("DDR0: Write Out-of-Range command\n");
break;
case (0x80000000>>13):
printf("Transfer error ack signal\n");
case 1:
printf("DDR0: Read Out-of-Range command\n");
break;
case (0x80000000>>14):
printf("Data parity signal\n");
case 2:
printf("DDR0: Masked write Out-of-Range command\n");
break;
case (0x80000000>>15):
printf("Address parity signal\n");
case 4:
printf("DDR0: Wrap write Out-of-Range command\n");
break;
case 5:
printf("DDR0: Wrap read Out-of-Range command\n");
break;
default:
printf("Unknown values in msr\n");
mfsdram(DDR0_01, value2);
printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
}
mfsdram(DDR0_23, val);
if ( (val >> 16) & 0xff)
printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
(val >> 16) & 0xff);
mfsdram(DDR0_23, val);
if ( (val >> 8) & 0xff)
printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
(val >> 8) & 0xff);
mfsdram(DDR0_33, val);
if (val)
printf("DDR0: Address of command that caused an "
"Out-of-Range interrupt %p\n", val);
mfsdram(DDR0_34, val);
if (val)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_35, val);
if (val)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_36, val);
if (val)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_37, val);
if (val)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_38, val);
if (val)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_39, val);
if (val)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_40, val);
if (val)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
mfsdram(DDR0_41, val);
if (val)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");
@ -224,7 +332,7 @@ ProgramCheckException(struct pt_regs *regs)
}
void
PITException(struct pt_regs *regs)
DecrementerPITException(struct pt_regs *regs)
{
/*
* Reset PIT interrupt
@ -272,17 +380,17 @@ addr_probe(uint *addr)
__asm__ __volatile__( \
"1: lwz %0,0(%1)\n" \
" eieio\n" \
" li %0,0\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: li %0,-1\n" \
" b 2b\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,3b\n" \
".text" \
: "=r" (retval) : "r"(addr));
" eieio\n" \
" li %0,0\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: li %0,-1\n" \
" b 2b\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,3b\n" \
".text" \
: "=r" (retval) : "r"(addr));
return (retval);
#endif

3
disk/part.c
View File

@ -180,7 +180,6 @@ void dev_print (block_dev_desc_t *dev_desc)
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
(CONFIG_COMMANDS & CFG_CMD_USB) || \
defined(CONFIG_MMC) || \
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
defined(CONFIG_SYSTEMACE) )
#if defined(CONFIG_MAC_PARTITION) || \
@ -223,7 +222,7 @@ void init_part (block_dev_desc_t * dev_desc)
int get_partition_info (block_dev_desc_t *dev_desc, int part
, disk_partition_t *info)
{
switch (dev_desc->part_type) {
switch (dev_desc->part_type) {
#ifdef CONFIG_MAC_PARTITION
case PART_TYPE_MAC:
if (get_partition_info_mac(dev_desc,part,info) == 0) {

13
doc/README.ppc440
View File

@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O
space begins at PCI I/O address 0 and the PCI memory space is
256 MB starting at PCI address CFG_PCI_TARGBASE. After the
pci_controller structure is initialized, the cpu-specific code will
call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
defined. This routine is implemented by board-specific code & is where
the board can over-ride/extend the default pci_controller structure
settings and do other pre-initialization tasks. If pci_pre_init()
returns a value of zero, PCI initialization is aborted; otherwise the
controller structure is registered and initialization continues.
call the routine pci_pre_init(). This routine is implemented by
board-specific code & is where the board can over-ride/extend the
default pci_controller structure settings and exspecially provide
a routine to map the PCI interrupts and do other pre-initialization
tasks. If pci_pre_init() returns a value of zero, PCI initialization
is aborted; otherwise the controller structure is registered and
initialization continues.
The default 440GP PCI target configuration is minimal -- it assumes that
the strapping registers are set as necessary. Since the strapping bits

2
drivers/Makefile
View File

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdrivers.a
COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o enc28j60.o \

216
drivers/ata_piix.c 100644
View File

@ -0,0 +1,216 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to ata_piix driver in kernel 2.4.32
*/
/*
* This file contains SATA controller and SATA drive initialization functions
*/
#include <common.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_ATA_PIIX /*ata_piix driver */
#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
#define DRV_DECL /*For file specific declarations */
#include <sata.h>
#undef DRV_DECL
/*Macros realted to PCI*/
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PCI_SATA_BASE1 0x10
#define PCI_SATA_BASE2 0x14
#define PCI_SATA_BASE3 0x18
#define PCI_SATA_BASE4 0x1c
#define PCI_SATA_BASE5 0x20
#define PCI_PMR 0x90
#define PCI_PI 0x09
#define PCI_PCS 0x92
#define PCI_DMA_CTL 0x48
#define PORT_PRESENT (1<<0)
#define PORT_ENABLED (1<<4)
u32 bdf;
u32 iobase1 = 0; /*Primary cmd block */
u32 iobase2 = 0; /*Primary ctl block */
u32 iobase3 = 0; /*Sec cmd block */
u32 iobase4 = 0; /*sec ctl block */
u32 iobase5 = 0; /*BMDMA*/
int
pci_sata_init (void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
u8 pmr; /*Port mapping reg */
u8 pi; /*Prgming Interface reg */
bdf = PCI_BDF (bus, dev, fun);
pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
printf ("error no base addr for SATA controller\n");
return 1;
/*ERROR*/}
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase3 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
/*check for mode */
pci_read_config_byte (bdf, PCI_PMR, &pmr);
if (pmr > 1) {
printf ("combined mode not supported\n");
return 1;
}
pci_read_config_byte (bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
printf ("Sata is in Legacy mode\n");
return 1;
} else {
printf ("sata is in Native mode\n");
}
/*MASTER CFG AND IO CFG */
pci_read_config_word (bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_word (bdf, PCI_COMMAND, cmd);
pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
return 0;
}
int
sata_bus_probe (int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
pci_read_config_word (bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
else
return 1;
}
int
init_sata (void)
{
u8 i, rv = 0;
for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
sata_dev_desc[i].if_type = IF_TYPE_IDE;
sata_dev_desc[i].dev = i;
sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
sata_dev_desc[i].blksz = 0;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].block_read = sata_read;
}
rv = pci_sata_init ();
if (rv == 1) {
printf ("pci initialization failed\n");
return 1;
}
port[0].port_no = 0;
port[0].ioaddr.cmd_addr = iobase1;
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
iobase2 | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase5;
port[1].port_no = 1;
port[1].ioaddr.cmd_addr = iobase3;
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
iobase4 | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CFG_SATA_MAXBUS; i++)
sata_port (&port[i].ioaddr);
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
if (!(sata_bus_probe (i))) {
port[i].port_state = 0;
printf ("SATA#%d port is not present \n", i);
} else {
printf ("SATA#%d port is present\n", i);
if (sata_bus_softreset (i)) {
port[i].port_state = 0;
} else {
port[i].port_state = 1;
}
}
}
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
u8 j, devno;
if (port[i].port_state == 0)
continue;
for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
sata_identify (i, j);
set_Feature_cmd (i, j);
devno = i * CFG_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
dev_print (&sata_dev_desc[devno]);
/* initialize partition type */
init_part (&sata_dev_desc[devno]);
if (curr_dev < 0)
curr_dev =
i * CFG_SATA_DEVS_PER_BUS + j;
}
}
}
return 0;
}
#endif

46
drivers/tsec.c
View File

@ -65,33 +65,31 @@ struct tsec_info_struct {
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
#if defined(CONFIG_MPC8544DS)
#if defined(CONFIG_TSEC1)
#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif
#elif defined(CONFIG_MPC86XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#elif defined(CONFIG_MPC86XX_TSEC2)
#if defined(CONFIG_TSEC2)
#if defined(CONFIG_MPC8641HPCN)
{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#endif
{0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
#if defined(CONFIG_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
#else
{0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
#if defined(CONFIG_TSEC4)
{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
#else
{0, 0, 0},
@ -928,6 +926,33 @@ struct phy_info phy_info_BCM5461S = {
},
};
struct phy_info phy_info_BCM5464S = {
0x02060b1, /* 5464 ID */
"Broadcom BCM5464S",
0, /* not clear to me what minor revisions we can shift away */
(struct phy_cmd[]) { /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
/* Status is read once to clear old link state */
{MIIM_STATUS, miim_read, NULL},
/* Auto-negotiate */
{MIIM_STATUS, miim_read, &mii_parse_sr},
/* Read the status */
{MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
{miim_end,}
},
};
struct phy_info phy_info_M88E1011S = {
0x01410c6,
"Marvell 88E1011S",
@ -1292,6 +1317,7 @@ struct phy_info *phy_info[] = {
&phy_info_cis8204,
&phy_info_cis8201,
&phy_info_BCM5461S,
&phy_info_BCM5464S,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
&phy_info_M88E1145,

42
fs/fat/fat.c
View File

@ -70,10 +70,11 @@ int
fat_register_device(block_dev_desc_t *dev_desc, int part_no)
{
unsigned char buffer[SECTOR_SIZE];
disk_partition_t info;
if (!dev_desc->block_read)
return -1;
cur_dev=dev_desc;
cur_dev = dev_desc;
/* check if we have a MBR (on floppies we have only a PBR) */
if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
printf ("** Can't read from device %d **\n", dev_desc->dev);
@ -84,36 +85,39 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
/* no signature found */
return -1;
}
if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset=0;
}
else {
#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
(CONFIG_COMMANDS & CFG_CMD_USB) || \
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
(defined(CONFIG_MMC)) || \
defined(CONFIG_SYSTEMACE) )
disk_partition_t info;
if(!get_partition_info(dev_desc, part_no, &info)) {
part_offset = info.start;
cur_part = part_no;
}
else {
printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev);
return -1;
}
/* First we assume, there is a MBR */
if (!get_partition_info (dev_desc, part_no, &info)) {
part_offset = info.start;
cur_part = part_no;
} else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset = 0;
} else {
printf ("** Partition %d not valid on device %d **\n", part_no, dev_desc->dev);
return -1;
}
#else
if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
/* ok, we assume we are on a PBR only */
cur_part = 1;
part_offset = 0;
info.start = part_offset;
} else {
/* FIXME we need to determine the start block of the
* partition where the DOS FS resides. This can be done
* by using the get_partition_info routine. For this
* purpose the libpart must be included.
*/
part_offset=32;
part_offset = 32;
cur_part = 1;
#endif
}
#endif
return 0;
}

1
include/74xx_7xx.h
View File

@ -34,6 +34,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values

8
include/asm-ppc/gpio.h
View File

@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
gpio_out_t out_val;/* Default Output Value */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);

61
include/asm-ppc/processor.h
View File

@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@ -123,9 +123,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@ -266,7 +266,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@ -308,7 +308,7 @@
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
@ -451,6 +451,17 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
@ -484,17 +495,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@ -511,13 +522,13 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
@ -529,7 +540,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@ -544,6 +555,8 @@
#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
#define SVR SPRN_SVR /* System Version Register */
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
@ -598,7 +611,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@ -607,7 +620,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@ -619,7 +632,7 @@
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@ -676,8 +689,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@ -802,7 +815,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*

60
include/ata.h
View File

@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
enum {
ATA_MAX_DEVICES = 1, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 256, /*256 words per sector */
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
/*ATA_LBA = (1 << 6), */ /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_PCI_CTL_OFS = 0x02,
/* and their aliases */
ATA_REG_FEATURE = ATA_REG_ERR,
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00
};
/*
* ATA Commands (only mandatory commands listed here)
*/

9
include/common.h
View File

@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char;
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
@ -248,10 +248,11 @@ void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller * );
# endif
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif

4
include/configs/CPCI405.h
View File

@ -55,6 +55,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \

5
include/configs/CPCI4052.h
View File

@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@ -56,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405AB.h
View File

@ -57,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405DT.h
View File

@ -56,6 +56,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

1
include/configs/CPCI440.h
View File

@ -33,6 +33,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */

1
include/configs/JSE.h
View File

@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000
#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */

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