sh: Add SH7269 device and RSK2+SH7269 board
This is an sh2a device (max 266MHz) with FPU, video display controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports, SD and on-chip USB. The RSK2+SH7269 board uses the SH7269 processor. It is often referred to as just rsk7269. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>utp
Phil Edworthy
Nobuhiro Iwamatsu
parent
a80a661989
commit
99744b7e34
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@ -35,6 +35,8 @@
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# include <asm/cpu_sh7203.h>
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#elif defined(CONFIG_CPU_SH7264)
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# include <asm/cpu_sh7264.h>
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#elif defined(CONFIG_CPU_SH7269)
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# include <asm/cpu_sh7269.h>
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#else
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# error "Unknown SH2 variant"
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#endif
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@ -0,0 +1,26 @@
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#ifndef _ASM_CPU_SH7269_H_
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#define _ASM_CPU_SH7269_H_
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/* Cache */
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#define CCR1 0xFFFC1000
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#define CCR CCR1
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/* SCIF */
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#define SCSMR_0 0xE8007000
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#define SCIF0_BASE SCSMR_0
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#define SCSMR_1 0xE8007800
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#define SCIF1_BASE SCSMR_1
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#define SCSMR_2 0xE8008000
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#define SCIF2_BASE SCSMR_2
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#define SCSMR_3 0xE8008800
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#define SCIF3_BASE SCSMR_3
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#define SCSMR_7 0xE800A800
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#define SCIF7_BASE SCSMR_7
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/* Timer(CMT) */
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#define CMSTR 0xFFFEC000
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#define CMCSR_0 0xFFFEC002
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#define CMCNT_0 0xFFFEC004
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#define CMCOR_0 0xFFFEC006
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#endif /* _ASM_CPU_SH7269_H_ */
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@ -0,0 +1,27 @@
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#
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# Copyright (C) 2012 Renesas Electronics Europe Ltd.
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# Copyright (C) 2012 Phil Edworthy
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#
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# This file is released under the terms of GPL v2 and any later version.
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# See the file COPYING in the root directory of the source tree for details.
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).o
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OBJS := rsk7269.o
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SOBJS := lowlevel_init.o
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LIB := $(addprefix $(obj),$(LIB))
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OBJS := $(addprefix $(obj),$(OBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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@ -0,0 +1,182 @@
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/*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd.
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* Copyright (C) 2012 Phil Edworthy
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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*
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* Based on board/renesas/rsk7264/lowlevel_init.S
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* Flush and enable caches (data cache in write-through mode) */
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write32 CCR1_A ,CCR1_D
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/* Disable WDT */
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write16 WTCSR_A, WTCSR_D
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write16 WTCNT_A, WTCNT_D
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/* Disable Register Bank interrupts */
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write16 IBNR_A, IBNR_D
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/* Set clocks based on 13.225MHz xtal */
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write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
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/* Enable all peripherals */
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write8 STBCR3_A, STBCR3_D
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write8 STBCR4_A, STBCR4_D
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write8 STBCR5_A, STBCR5_D
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write8 STBCR6_A, STBCR6_D
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write8 STBCR7_A, STBCR7_D
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write8 STBCR8_A, STBCR8_D
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write8 STBCR9_A, STBCR9_D
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write8 STBCR10_A, STBCR10_D
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/* SCIF7 and IIC2 */
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write16 PJCR3_A, PJCR3_D /* TXD7 */
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write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
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/* Configure bus (CS0) */
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write16 PFCR3_A, PFCR3_D /* A24 */
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write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
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write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
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write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
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write32 CS0WCR_A, CS0WCR_D
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write32 CS0BCR_A, CS0BCR_D
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/* Configure SDRAM (CS3) */
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write16 PCCR2_A, PCCR2_D /* CS3# */
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write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
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write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
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write32 CS3BCR_A, CS3BCR_D
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write32 CS3WCR_A, CS3WCR_D
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write32 SDCR_A, SDCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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/* Configure ethernet (CS1) */
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write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
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write16 PHCR0_A, PHCR0_D
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write16 PFCR2_A, PFCR2_D /* CS1# */
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write32 CS1BCR_A, CS1BCR_D /* Big endian */
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write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
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write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
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write16 PJIOR1_A, PJIOR1_D
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/* wait 200us */
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mov.l REPEAT_D, r3
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mov #0, r2
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repeat0:
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add #1, r2
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cmp/hs r3, r2
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bf repeat0
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nop
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mov.l SDRAM_MODE, r1
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mov #0, r0
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mov.l r0, @r1
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nop
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rts
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.align 4
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CCR1_A: .long CCR1
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CCR1_D: .long 0x0000090B
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STBCR3_A: .long 0xFFFE0408
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STBCR4_A: .long 0xFFFE040C
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STBCR5_A: .long 0xFFFE0410
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STBCR6_A: .long 0xFFFE0414
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STBCR7_A: .long 0xFFFE0418
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STBCR8_A: .long 0xFFFE041C
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STBCR9_A: .long 0xFFFE0440
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STBCR10_A: .long 0xFFFE0444
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STBCR3_D: .long 0x0000001A
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STBCR4_D: .long 0x00000000
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STBCR5_D: .long 0x00000000
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STBCR6_D: .long 0x00000000
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STBCR7_D: .long 0x00000012
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STBCR8_D: .long 0x00000009
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STBCR9_D: .long 0x00000000
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STBCR10_D: .long 0x00000010
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WTCSR_A: .long 0xFFFE0000
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WTCNT_A: .long 0xFFFE0002
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WTCSR_D: .word 0xA518
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WTCNT_D: .word 0x5A00
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IBNR_A: .long 0xFFFE080E
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IBNR_D: .word 0x0000
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.align 2
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FRQCR_A: .long 0xFFFE0010
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FRQCR_D: .word 0x0015
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.align 2
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PJCR3_A: .long 0xFFFE3908
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PJCR3_D: .word 0x5000
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.align 2
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PECR1_A: .long 0xFFFE388C
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PECR1_D: .word 0x2011
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.align 2
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PFCR3_A: .long 0xFFFE38A8
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PFCR2_A: .long 0xFFFE38AA
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PBCR5_A: .long 0xFFFE3824
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PFCR3_D: .word 0x0010
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PFCR2_D: .word 0x0101
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PBCR5_D: .word 0x0111
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.align 2
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CS0WCR_A: .long 0xFFFC0028
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CS0WCR_D: .long 0x00000341
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CS0BCR_A: .long 0xFFFC0004
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CS0BCR_D: .long 0x00000400
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PCCR2_A: .long 0xFFFE384A
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PCCR1_A: .long 0xFFFE384C
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PCCR0_A: .long 0xFFFE384E
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PCCR2_D: .word 0x0001
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PCCR1_D: .word 0x1111
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PCCR0_D: .word 0x1111
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.align 2
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CS3BCR_A: .long 0xFFFC0010
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CS3BCR_D: .long 0x00004400
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CS3WCR_A: .long 0xFFFC0034
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CS3WCR_D: .long 0x00004912
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SDCR_A: .long 0xFFFC004C
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SDCR_D: .long 0x00000811
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RTCOR_A: .long 0xFFFC0058
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RTCOR_D: .long 0xA55A0035
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RTCSR_A: .long 0xFFFC0050
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RTCSR_D: .long 0xA55A0010
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.align 2
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SDRAM_MODE: .long 0xFFFC5460
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REPEAT_D: .long 0x000033F1
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PHCR1_A: .long 0xFFFE38EC
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PHCR0_A: .long 0xFFFE38EE
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PHCR1_D: .word 0x2222
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PHCR0_D: .word 0x2222
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.align 2
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CS1BCR_A: .long 0xFFFC0008
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CS1BCR_D: .long 0x00000400
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CS1WCR_A: .long 0xFFFC002C
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CS1WCR_D: .long 0x00000080
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PJDR1_A: .long 0xFFFE3914
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PJDR1_D: .word 0x0000
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.align 2
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PJIOR1_A: .long 0xFFFE3910
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PJIOR1_D: .word 0x8000
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.align 2
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@ -0,0 +1,73 @@
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/*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd.
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* Copyright (C) 2012 Phil Edworthy
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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*
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* Based on u-boot/board/rsk7264/rsk7264.c
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("BOARD: Renesas RSK7269\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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/*
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* The RSK board has the SMSC89218 wired up 'incorrectly'.
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* Byte-swapping is necessary, and so poor performance is inevitable.
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* This problem cannot evade by the swap function of CHIP, this can
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* evade by software Byte-swapping.
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* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
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* functions necessary to solve this problem.
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*/
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u32 pkt_data_pull(struct eth_device *dev, u32 addr)
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{
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volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
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return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
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| swab16(*(addr_16 + 1));
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}
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void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
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{
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addr += dev->iobase;
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*(volatile u16 *)(addr + 2) = swab16((u16)val);
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*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -1013,6 +1013,7 @@ xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx
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sandbox sandbox sandbox sandbox sandbox -
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rsk7203 sh sh2 rsk7203 renesas -
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rsk7264 sh sh2 rsk7264 renesas -
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rsk7269 sh sh2 rsk7269 renesas -
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mpr2 sh sh3 mpr2 - -
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ms7720se sh sh3 ms7720se - -
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shmin sh sh3 shmin - -
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@ -35,6 +35,10 @@
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# define SCIF_BASE SCIF4_BASE
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#elif defined(CONFIG_CONS_SCIF5)
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# define SCIF_BASE SCIF5_BASE
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#elif defined(CONFIG_CONS_SCIF6)
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# define SCIF_BASE SCIF6_BASE
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#elif defined(CONFIG_CONS_SCIF7)
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# define SCIF_BASE SCIF7_BASE
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#else
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# error "Default SCIF doesn't set....."
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#endif
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@ -199,6 +199,16 @@ struct uart_port {
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# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
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# endif
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7269)
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# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
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# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
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# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
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# define SCSPTR3 0xe8008820 /* 16 bit SCIF */
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# define SCSPTR4 0xe8009020 /* 16 bit SCIF */
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# define SCSPTR5 0xe8009820 /* 16 bit SCIF */
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# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
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# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7619)
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# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
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# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
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@ -0,0 +1,76 @@
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/*
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* Configuation settings for the Renesas RSK2+SH7269 board
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*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd.
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* Copyright (C) 2012 Phil Edworthy
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#ifndef __RSK7269_H
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#define __RSK7269_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH2 1
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#define CONFIG_SH2A 1
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#define CONFIG_CPU_SH7269 1
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#define CONFIG_RSK7269 1
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#ifndef _CONFIG_CMD_DEFAULT_H
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# include <config_cmd_default.h>
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS "console=ttySC7,115200"
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Boot Argument Buffer Size */
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#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Serial */
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#define CONFIG_SCIF_CONSOLE
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#define CONFIG_CONS_SCIF7
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/* Memory */
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/* u-boot relocated to top 256KB of ram */
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#define CONFIG_SYS_TEXT_BASE 0x0DFC0000
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#define CONFIG_SYS_SDRAM_BASE 0x0C000000
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#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
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/* NOR Flash */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET (128 * 1024)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 66125000
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||||
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
|
||||
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
|
||||
|
||||
/* Network interface */
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
#define CONFIG_SMC911X_BASE 0x24000000
|
||||
|
||||
#endif /* __RSK7269_H */
|
||||
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Reference in New Issue