mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
1f5cb79374
commit
9a9865508f
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@ -85,8 +85,8 @@
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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@ -106,13 +106,16 @@
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#define CONFIG_DDR_II
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10 \
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| CSCONFIG_ODT_WR_ACS)
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_ECC_EN)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(1115 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
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| (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_MODE 0x47800432
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#define CONFIG_SYS_DDR_MODE2 0x8000c000
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@ -125,14 +128,14 @@
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
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( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
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( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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( 3 << TIMING_CFG1_WRREC_SHIFT) | \
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(10 << TIMING_CFG1_REFREC_SHIFT) | \
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( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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( 3 << TIMING_CFG1_PRETOACT_SHIFT))
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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@ -163,8 +166,8 @@
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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@ -172,33 +175,40 @@
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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@ -230,8 +240,9 @@
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#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
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/* Port size 32 bit, UPMB */
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
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#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
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/* PS=11, UPMB */
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
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#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
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/*
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* Serial Port
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@ -243,13 +254,13 @@
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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@ -268,9 +279,9 @@
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* General PCI
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@ -284,9 +295,9 @@
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
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#ifdef CONFIG_PCI
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@ -312,8 +323,8 @@
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
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#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 2
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
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#endif
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#define CONFIG_UEC_ETH2 /* GETH2 */
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
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#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 4
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
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#endif
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/*
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@ -334,11 +345,11 @@
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x20000
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#else /* CONFIG_SYS_RAMBOOT */
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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@ -390,17 +401,19 @@
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/*
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* Core HID Setup
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@ -417,54 +430,95 @@
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
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| BATU_BL_4M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* NAND: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
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| BATU_BL_64M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
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| BATU_BL_32M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
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| BATL_PP_10)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
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| BATU_BL_64M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
|
||||
| BATL_PP_10 \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
#else /* CONFIG_PCI */
|
||||
|
|
@ -507,49 +561,51 @@
|
|||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0"\
|
||||
"consoledev=ttyS0\0"\
|
||||
"loadaddr=a00000\0"\
|
||||
"fdtaddr=900000\0"\
|
||||
"fdtfile=mpc836x_rdk.dtb\0"\
|
||||
"fsfile=fs\0"\
|
||||
"ubootfile=u-boot.bin\0"\
|
||||
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
|
||||
"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
|
||||
"$mtdparts panic=1\0"\
|
||||
"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
|
||||
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
|
||||
"$gatewayip:$netmask:$hostname:$netdev:off "\
|
||||
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
|
||||
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
|
||||
"rootfstype=jffs2 rw\0"\
|
||||
"tftp_get_uboot=tftp 100000 $ubootfile\0"\
|
||||
"tftp_get_kernel=tftp $loadaddr $bootfile\0"\
|
||||
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
|
||||
"tftp_get_fs=tftp c00000 $fsfile\0"\
|
||||
"nand_erase_kernel=nand erase 0 400000\0"\
|
||||
"nand_erase_dtb=nand erase 400000 20000\0"\
|
||||
"nand_erase_fs=nand erase 420000 3be0000\0"\
|
||||
"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
|
||||
"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
|
||||
"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
|
||||
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
|
||||
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
|
||||
"nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
|
||||
"cp.b 100000 ff800000 $filesize\0"\
|
||||
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
|
||||
"nand_write_kernel\0"\
|
||||
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
|
||||
"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
|
||||
"nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
|
||||
"nand_reflash_fs\0"\
|
||||
"boot_m=bootm $loadaddr - $fdtaddr\0"\
|
||||
"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
|
||||
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
|
||||
"boot_m\0"\
|
||||
"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
|
||||
"boot_m\0"\
|
||||
""
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"loadaddr=a00000\0" \
|
||||
"fdtaddr=900000\0" \
|
||||
"fdtfile=mpc836x_rdk.dtb\0" \
|
||||
"fsfile=fs\0" \
|
||||
"ubootfile=u-boot.bin\0" \
|
||||
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
|
||||
"-(rootfs)\0" \
|
||||
"setbootargs=setenv bootargs console=$consoledev,$baudrate " \
|
||||
"$mtdparts panic=1\0" \
|
||||
"adddhcpargs=setenv bootargs $bootargs ip=on\0" \
|
||||
"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
|
||||
"$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
|
||||
"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
|
||||
"rootfstype=jffs2 rw\0" \
|
||||
"tftp_get_uboot=tftp 100000 $ubootfile\0" \
|
||||
"tftp_get_kernel=tftp $loadaddr $bootfile\0" \
|
||||
"tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
|
||||
"tftp_get_fs=tftp c00000 $fsfile\0" \
|
||||
"nand_erase_kernel=nand erase 0 400000\0" \
|
||||
"nand_erase_dtb=nand erase 400000 20000\0" \
|
||||
"nand_erase_fs=nand erase 420000 3be0000\0" \
|
||||
"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
|
||||
"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
|
||||
"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
|
||||
"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
|
||||
"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
|
||||
"nor_reflash=protect off ff800000 ff87ffff ; " \
|
||||
"erase ff800000 ff87ffff ; " \
|
||||
"cp.b 100000 ff800000 $filesize\0" \
|
||||
"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
|
||||
"nand_write_kernel\0" \
|
||||
"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
|
||||
"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
|
||||
"nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
|
||||
"nand_reflash_fs\0" \
|
||||
"boot_m=bootm $loadaddr - $fdtaddr\0" \
|
||||
"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
|
||||
"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
|
||||
"boot_m\0" \
|
||||
"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
|
||||
"boot_m\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run dhcpboot"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue