redonkable/remarkable-uboot
redonkable/remarkable-uboot
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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

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This commit is contained in:
Wolfgang Denk 2009-09-30 23:26:59 +02:00
parent 7b5ae460c3 b306db2f1b
commit 9ae7ae6b4d
85 changed files with 1306 additions and 1336 deletions
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12
board/amcc/acadia/acadia.c
View file

@ -78,12 +78,12 @@ int board_early_init_f(void)
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

28
board/amcc/bamboo/bamboo.c
View file

@ -392,21 +392,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins

12
board/amcc/bubinga/bubinga.c
View file

@ -29,12 +29,12 @@ long int spd_sdram(void);
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000010);
mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000010);
mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Configure CPC0_PCI to enable PerWE as output

56
board/amcc/canyonlands/canyonlands.c
View file

@ -116,37 +116,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */

52
board/amcc/ebony/ebony.c
View file

@ -71,21 +71,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}
@ -131,11 +131,11 @@ long int fixed_sdram(void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@ -143,20 +143,20 @@ long int fixed_sdram(void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram(mem_mcsts, reg);
mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}

64
board/amcc/katmai/katmai.c
View file

@ -183,42 +183,42 @@ int board_early_init_f (void)
* Set critical interrupt values. Set interrupt polarities. Set interrupt
* trigger levels. Make bit 0 High priority. Clear all interrupts again.
*------------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

48
board/amcc/kilauea/kilauea.c
View file

@ -158,33 +158,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so

32
board/amcc/luan/luan.c
View file

@ -49,23 +49,23 @@ int board_early_init_f(void)
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic1sr, 0xffffffff );
mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC1SR, 0xffffffff );
mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
mtdcr( UIC0SR, 0xffffffff );
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

48
board/amcc/makalu/makalu.c
View file

@ -159,33 +159,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so

78
board/amcc/ocotea/ocotea.c
View file

@ -159,36 +159,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(SDR0_MFR, mfr); */
@ -241,11 +241,11 @@ long int fixed_sdram (void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@ -253,20 +253,20 @@ long int fixed_sdram (void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}

56
board/amcc/redwood/redwood.c
View file

@ -416,41 +416,41 @@ static void early_init_UIC(void)
* interrupt trigger levels. Make bit 0 High priority. Clear all
* interrupts again.
*/
mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic3er, 0x00000000); /* disable all interrupts */
mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic2er, 0x00000000); /* disable all interrupts */
mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic1er, 0x00000000); /* disable all interrupts */
mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
}

42
board/amcc/sequoia/sequoia.c
View file

@ -52,29 +52,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* 50MHz tmrclk */
out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);

14
board/amcc/taihu/taihu.c
View file

@ -40,13 +40,13 @@ int board_early_init_f(void)
{
lcd_init();
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);

54
board/amcc/taishan/taishan.c
View file

@ -132,36 +132,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(SDR0_PFC0,reg);

14
board/amcc/walnut/walnut.c
View file

@ -47,13 +47,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004

60
board/amcc/yosemite/yosemite.c
View file

@ -82,21 +82,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
@ -237,7 +237,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i));
mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@ -289,15 +289,15 @@ phys_size_t initdram(int board)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@ -305,29 +305,29 @@ phys_size_t initdram(int board)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x80000000); /* Enable */
mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
mfsdram(SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
}

64
board/amcc/yucca/yucca.c
View file

@ -485,50 +485,50 @@ int board_early_init_f (void)
| interrupt trigger levels. Make bit 0 High priority. Clear all
| interrupts again.
+-------------------------------------------------------------------*/
mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic3er, 0x00000000); /* disable all interrupts */
mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic2er, 0x00000000); /* disable all interrupts */
mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic1er, 0x00000000); /* disable all interrupts */
mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

32
board/cray/L1/L1.c
View file

@ -113,13 +113,13 @@ int board_early_init_f (void)
{
/* Running from ROM: global data is still READONLY */
init_sdram ();
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
@ -198,7 +198,7 @@ static void init_sdram (void)
unsigned long tmp;
/* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
@ -212,25 +212,25 @@ static void init_sdram (void)
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
/* write SDRAM timing for 100MHz. */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200);
/* sdram controller.*/
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200);
/* initially, disable ECC on all banks */
udelay (200);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff;
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, tmp);
return;
@ -282,15 +282,15 @@ int testdram (void)
}
printf ("Enable ECC..");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
;
udelay (400);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000;
mtdcr (SDRAM0_CFGDATA, tmp);

22
board/csb272/csb272.c
View file

@ -87,13 +87,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
@ -135,28 +135,28 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

18
board/csb272/init.S
View file

@ -175,26 +175,26 @@ sdram_init:
* Disable memory controller to allow
* values to be changed.
*/
WDCR_SDRAM(mem_mcopt1, 0x00000000)
WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/*
* Configure Memory Banks
*/
WDCR_SDRAM(mem_mb0cf, 0x00084001)
WDCR_SDRAM(mem_mb1cf, 0x00000000)
WDCR_SDRAM(mem_mb2cf, 0x00000000)
WDCR_SDRAM(mem_mb3cf, 0x00000000)
WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
WDCR_SDRAM(mem_sdtr1, 0x00854009)
WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
WDCR_SDRAM(mem_rtr, 0x10000000)
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */
WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
/* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
@ -210,7 +210,7 @@ sdram_init:
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
WDCR_SDRAM(mem_mcopt1,0x80800000)
WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done:
blr /* Return to calling function */

22
board/csb472/csb472.c
View file

@ -55,13 +55,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
@ -103,28 +103,28 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

18
board/csb472/init.S
View file

@ -171,26 +171,26 @@ sdram_init:
* Disable memory controller to allow
* values to be changed.
*/
WDCR_SDRAM(mem_mcopt1, 0x00000000)
WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
/*
* Configure Memory Banks
*/
WDCR_SDRAM(mem_mb0cf, 0x00062001)
WDCR_SDRAM(mem_mb1cf, 0x00000000)
WDCR_SDRAM(mem_mb2cf, 0x00000000)
WDCR_SDRAM(mem_mb3cf, 0x00000000)
WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
WDCR_SDRAM(mem_sdtr1, 0x00854009)
WDCR_SDRAM(SDRAM0_TR, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
WDCR_SDRAM(mem_rtr, 0x10000000)
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */
WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
/* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
@ -206,7 +206,7 @@ sdram_init:
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
WDCR_SDRAM(mem_mcopt1,0x80800000)
WDCR_SDRAM(SDRAM0_CFG,0x80800000)
..sdri_done:
blr /* Return to calling function */

14
board/dave/PPChameleonEVB/PPChameleonEVB.c
View file

@ -53,13 +53,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5)
* IRQ 31 (EXT IRQ 6)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/eric/eric.c
View file

@ -62,13 +62,13 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels, UART0 is EDGE */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */

14
board/eric/init.S
View file

@ -228,7 +228,7 @@ sdram_init:
/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb0cf
addi r4,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB0CF@h
ori r4,r4,MB0CF@l
@ -238,7 +238,7 @@ sdram_init:
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb1cf
addi r4,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB1CF@h
ori r4,r4,MB1CF@l
@ -248,7 +248,7 @@ sdram_init:
/* Set MB2CF for bank 2. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb2cf
addi r4,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB2CF@h
ori r4,r4,MB2CF@l
@ -258,7 +258,7 @@ sdram_init:
/* Set MB3CF for bank 3. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb3cf
addi r4,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB3CF@h
ori r4,r4,MB3CF@l
@ -305,14 +305,14 @@ sdram_init:
/*------------------------------------------------------------------- */
/* Set SDTR1 */
/*------------------------------------------------------------------- */
addi r4,0,mem_sdtr1
addi r4,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r6
/*------------------------------------------------------------------- */
/* Set RTR */
/*------------------------------------------------------------------- */
addi r4,0,mem_rtr
addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
@ -332,7 +332,7 @@ sdram_init:
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
/*------------------------------------------------------------------- */
addi r4,0,mem_mcopt1
addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x8080 /* set DC_EN=1 */
ori r4,r4,0x0000

14
board/esd/apc405/apc405.c
View file

@ -155,13 +155,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

14
board/esd/ar405/ar405.c
View file

@ -130,13 +130,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */

14
board/esd/ash405/ash405.c
View file

@ -66,13 +66,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/canbt/canbt.c
View file

@ -134,13 +134,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/esd/cms700/cms700.c
View file

@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/cpci2dp/cpci2dp.c
View file

@ -58,14 +58,14 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) unused
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

18
board/esd/cpci405/cpci405.c
View file

@ -179,22 +179,22 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
}
#else
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
* INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

16
board/esd/cpciiser4/cpciiser4.c
View file

@ -129,14 +129,14 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
/* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
/* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}

14
board/esd/dp405/dp405.c
View file

@ -43,13 +43,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/du405/du405.c
View file

@ -124,13 +124,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 100 us

42
board/esd/du440/du440.c
View file

@ -87,37 +87,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
/*
* UIC1:
* bit30: ext. Irq 1: PLD : int 32+30
*/
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xfffffffd);
mtdcr(uic1tr, 0x00000000);
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xfffffffd);
mtdcr(UIC1TR, 0x00000000);
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*
* UIC2
* bit3: ext. Irq 2: DCF77 : int 64+3
*/
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);

14
board/esd/hh405/hh405.c
View file

@ -363,13 +363,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/hub405/hub405.c
View file

@ -86,13 +86,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/ocrtc/ocrtc.c
View file

@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: clear EBTC -> high-Z ebc signals between

16
board/esd/pci405/pci405.c
View file

@ -155,13 +155,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Setup GPIO pins (IRQ4/GPIO21 as GPIO)
@ -271,7 +271,7 @@ int misc_init_r (void)
pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
}
}
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
*magic = 0; /* clear pci reconfig magic again */
}

14
board/esd/plu405/plu405.c
View file

@ -78,13 +78,13 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to

14
board/esd/pmc405/pmc405.c
View file

@ -48,13 +48,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register:

14
board/esd/pmc405de/pmc405de.c
View file

@ -114,13 +114,13 @@ int board_early_init_f(void)
* IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register:

42
board/esd/pmc440/pmc440.c
View file

@ -148,29 +148,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ef);
mtdcr(uic0tr, 0x00000000);
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ef);
mtdcr(UIC0TR, 0x00000000);
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffc7f5);
mtdcr(uic1tr, 0x00000000);
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffc7f5);
mtdcr(UIC1TR, 0x00000000);
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27ffffff);
mtdcr(uic2tr, 0x00000000);
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0x27ffffff);
mtdcr(UIC2TR, 0x00000000);
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);

14
board/esd/voh405/voh405.c
View file

@ -88,13 +88,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/vom405/vom405.c
View file

@ -45,13 +45,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

14
board/esd/wuh405/wuh405.c
View file

@ -64,13 +64,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

22
board/exbitgen/exbitgen.c
View file

@ -37,13 +37,13 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* Perform reset of PHY connected to PPC via register in CPLD */
out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
@ -94,28 +94,28 @@ phys_size_t initdram (int board_type)
tot_size = 0;
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);

14
board/exbitgen/init.S
View file

@ -382,7 +382,7 @@ sdram_init:
/*----------------------------------------------------------- */
/* Set SDTR1 */
/*----------------------------------------------------------- */
addi r5,0,mem_sdtr1
addi r5,0,SDRAM0_TR
mtdcr SDRAM0_CFGADDR,r5
mtdcr SDRAM0_CFGDATA,r4
@ -413,7 +413,7 @@ sdram_init:
/* Set SDRAM bank 0 register and adjust r6 for next bank */
/*------------------------------------------------------ */
addi r7,0,mem_mb0cf
addi r7,0,SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@ -424,7 +424,7 @@ sdram_init:
cmpi 0, r12, 2
bne b1skip
addi r7,0,mem_mb1cf
addi r7,0,SDRAM0_B1CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@ -432,7 +432,7 @@ sdram_init:
/* Set SDRAM bank 2 register and adjust r6 for next bank */
/*------------------------------------------------------ */
b1skip: addi r7,0,mem_mb2cf
b1skip: addi r7,0,SDRAM0_B2CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
@ -443,7 +443,7 @@ b1skip: addi r7,0,mem_mb2cf
cmpi 0, r12, 2
bne b3skip
addi r7,0,mem_mb3cf
addi r7,0,SDRAM0_B3CR
mtdcr SDRAM0_CFGADDR,r7
mtdcr SDRAM0_CFGDATA,r6
b3skip:
@ -456,7 +456,7 @@ b3skip:
addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
bl rtr_2
rtr_1: addis r7, 0, 0x03F8
rtr_2: addi r4,0,mem_rtr
rtr_2: addi r4,0,SDRAM0_RTR
mtdcr SDRAM0_CFGADDR,r4
mtdcr SDRAM0_CFGDATA,r7
@ -476,7 +476,7 @@ rtr_2: addi r4,0,mem_rtr
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
/*----------------------------------------------------------- */
addi r4,0,mem_mcopt1
addi r4,0,SDRAM0_CFG
mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x80C0 /* set DC_EN=1 */
ori r4,r4,0x0000

41
board/g2000/g2000.c
View file

@ -38,20 +38,20 @@
int board_early_init_f (void)
{
#if 0 /* test-only */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000010);
mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr (uictr, 0x00000010); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000010);
mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#else
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
#endif
#if 1 /* test-only */
@ -114,18 +114,17 @@ int checkboard (void)
long int init_sdram_static_settings(void)
{
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
}

14
board/gdsys/dlvision/dlvision.c
View file

@ -36,13 +36,13 @@ enum {
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

28
board/gdsys/gdppc440etx/gdppc440etx.c
View file

@ -83,21 +83,21 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*
* Setup other serial configuration

56
board/gdsys/intip/intip.c
View file

@ -44,37 +44,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
/*
* Configure PFC (Pin Function Control) registers

14
board/gdsys/neo/neo.c
View file

@ -31,13 +31,13 @@
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks

12
board/jse/jse.c
View file

@ -48,12 +48,12 @@ int board_early_init_f (void)
| IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
| IRQ 31 (EXT IRQ 6) (unused)
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* Configure the interface to the SystemACE MCU port.
The SystemACE is fast, but there is no reason to have

36
board/jse/sdram.c
View file

@ -35,59 +35,59 @@ phys_size_t initdram (int board_type)
/* Configure the SDRAMS */
/* disable memory controller */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_besra);
mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_besrb);
mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtdcr (SDRAM0_CFGADDR, mem_eccerr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
mtdcr (SDRAM0_CFGDATA, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, 0x010a4016);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, 0x00084001);
/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, 0x04084001);
/* Memory Bank 2 Config == BE=0 */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* Memory Bank 3 Config == BE=0 */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, 0x00000000);
/* refresh timer = 0x400 */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, 0x04000000);
/* Power management idle timer set to the default. */
mtdcr (SDRAM0_CFGADDR, mem_pmit);
mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
mtdcr (SDRAM0_CFGDATA, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, 0x80e00000);
return SDRAM_LEN;
@ -108,7 +108,7 @@ int testdram (void)
#ifdef DEBUG
printf ("SDRAM Controller Registers --\n");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_CFG : 0x%08x\n", val);
@ -116,19 +116,19 @@ int testdram (void)
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_STATUS: 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B0CR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_B1CR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_TR : 0x%08x\n", val);
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
val = mfdcr (SDRAM0_CFGDATA);
printf (" SDRAM0_RTR : 0x%08x\n", val);
#endif

42
board/korat/korat.c
View file

@ -87,29 +87,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/*
* Take sim card reader and CF controller out of reset. Also enable PHY

42
board/lwmon5/lwmon5.c
View file

@ -44,29 +44,29 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* Trace Pins are disabled. SDR0_PFC0 Register */
mtsdr(SDR0_PFC0, 0x0);

52
board/mpl/mip405/mip405.c
View file

@ -348,7 +348,7 @@ int init_sdram (void)
/* trc_clocks is sum of trp_clocks + tras_clocks */
trc_clocks = trp_clocks + tras_clocks;
/* get SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
sdram_tim |= ((unsigned long) (cal_val)) << 23;
@ -369,7 +369,7 @@ int init_sdram (void)
/* insert SZ value; */
tmp |= ((unsigned long) sdram_table[i].sz << 17);
/* get SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_bank |= (baseaddr | tmp | 0x01);
@ -380,7 +380,7 @@ int init_sdram (void)
#endif
/* write SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, sdram_tim);
#ifdef SDRAM_DEBUG
@ -390,22 +390,22 @@ int init_sdram (void)
#endif
/* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, sdram_bank);
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
/* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x07F00000;
} else {
/* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
tmp |= 0x05F00000;
}
/* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
@ -415,18 +415,18 @@ int init_sdram (void)
#ifdef SDRAM_DEBUG
serial_puts ("disable ECC.. ");
#endif
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff; /* disable all banks */
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
/* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG
serial_puts ("setup SDRAM Controller.. ");
#endif
mtdcr (SDRAM0_CFGDATA, tmp);
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (600);
#ifdef SDRAM_DEBUG
@ -447,7 +447,7 @@ int init_sdram (void)
serial_puts ("enable ECC\n");
#endif
udelay (400);
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000; /* enable bank 0 */
mtdcr (SDRAM0_CFGDATA, tmp);
@ -456,9 +456,9 @@ int init_sdram (void)
#endif
{
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
}
@ -489,13 +489,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
@ -631,13 +631,13 @@ phys_size_t initdram (int board_type)
ds = 0;
/* since the DRAM controller is allready set up, calculate the size with the
bank registers */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {
@ -648,7 +648,7 @@ phys_size_t initdram (int board_type)
} else
ds = 1;
}
mtdcr (SDRAM0_CFGADDR, mem_ecccf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
tmp = mfdcr (SDRAM0_CFGDATA);
if (!tmp)

50
board/mpl/pip405/pip405.c
View file

@ -361,7 +361,7 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
/* get SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
/* insert CASL value */
/* tmp |= ((unsigned long)cal_val) << 23; */
@ -385,7 +385,7 @@ int board_early_init_f (void)
#endif
/* write SDRAM timing register */
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
mtdcr (SDRAM0_CFGDATA, tmp);
baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
@ -418,7 +418,7 @@ int board_early_init_f (void)
SDRAM_err ("unsupported SDRAM");
} /* endswitch */
/* get SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
@ -434,11 +434,11 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 0 register */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 1 register */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
sdram_size = 0;
@ -459,11 +459,11 @@ int board_early_init_f (void)
serial_puts ("\n");
#endif
/* write SDRAM bank 1 register */
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 2 register */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
bank |= (baseaddr | tmp | 0x01);
@ -482,11 +482,11 @@ int board_early_init_f (void)
sdram_size += bank_size;
/* write SDRAM bank 2 register */
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM bank 3 register */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
#ifdef SDRAM_DEBUG
@ -509,12 +509,12 @@ int board_early_init_f (void)
#endif
/* write SDRAM bank 3 register */
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
mtdcr (SDRAM0_CFGDATA, bank);
/* get SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
if (tmemclk < NSto10PS (16))
@ -523,13 +523,13 @@ int board_early_init_f (void)
tmp |= 0x03F80000;
/* write SDRAM refresh interval register */
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
mtdcr (SDRAM0_CFGDATA, tmp);
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
mtdcr (SDRAM0_CFGDATA, tmp);
@ -552,13 +552,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
@ -619,13 +619,13 @@ phys_size_t initdram (int board_type)
/* since the DRAM controller is allready set up,
* calculate the size with the bank registers
*/
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
TotalSize = 0;
for (i = 0; i < 4; i++) {

40
board/netstal/common/fixed_sdram.c
View file

@ -29,17 +29,17 @@ void show_sdram_registers(void)
u32 value;
printf("SDRAM Controller Registers --\n");
mfsdram(mem_mcopt1, value);
mfsdram(SDRAM0_CFG, value);
printf(" SDRAM0_CFG : 0x%08x\n", value);
mfsdram(mem_status, value);
mfsdram(SDRAM0_STATUS, value);
printf(" SDRAM0_STATUS: 0x%08x\n", value);
mfsdram(mem_mb0cf, value);
mfsdram(SDRAM0_B0CR, value);
printf(" SDRAM0_B0CR : 0x%08x\n", value);
mfsdram(mem_mb1cf, value);
mfsdram(SDRAM0_B1CR, value);
printf(" SDRAM0_B1CR : 0x%08x\n", value);
mfsdram(mem_sdtr1, value);
mfsdram(SDRAM0_TR, value);
printf(" SDRAM0_TR : 0x%08x\n", value);
mfsdram(mem_rtr, value);
mfsdram(SDRAM0_RTR, value);
printf(" SDRAM0_RTR : 0x%08x\n", value);
}
#endif
@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size)
printf(__FUNCTION__);
#endif
/* disable memory controller */
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(SDRAM0_CFG, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtsdram(mem_besra, 0xffffffff);
mtsdram(SDRAM0_BESR0, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtsdram(mem_besrb, 0xffffffff);
mtsdram(SDRAM0_BESR1, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
mtsdram(mem_ecccf, 0x00000000);
mtsdram(SDRAM0_ECCCFG, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtsdram(mem_eccerr, 0xffffffff);
mtsdram(SDRAM0_ECCESR, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
*/
mtsdram(mem_sdtr1, 0x008a4015);
mtsdram(SDRAM0_TR, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* and refresh timer
*/
switch (dram_size >> 20) {
case 32:
mtsdram(mem_mb0cf, 0x00062001);
mtsdram(mem_rtr, 0x07F00000);
mtsdram(SDRAM0_B0CR, 0x00062001);
mtsdram(SDRAM0_RTR, 0x07F00000);
break;
case 64:
mtsdram(mem_mb0cf, 0x00084001);
mtsdram(mem_rtr, 0x04100000);
mtsdram(SDRAM0_B0CR, 0x00084001);
mtsdram(SDRAM0_RTR, 0x04100000);
break;
case 128:
mtsdram(mem_mb0cf, 0x000A4001);
mtsdram(mem_rtr, 0x04100000);
mtsdram(SDRAM0_B0CR, 0x000A4001);
mtsdram(SDRAM0_RTR, 0x04100000);
break;
default:
printf("Invalid memory size of %d MB given\n", dram_size >> 20);
}
/* Power management idle timer set to the default. */
mtsdram(mem_pmit, 0x07c00000);
mtsdram(SDRAM0_PMIT, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
mtsdram(mem_mcopt1, 0x90800000);
mtsdram(SDRAM0_CFG, 0x90800000);
#ifdef DEBUG
printf("%s: done\n", __FUNCTION__);

12
board/netstal/hcu4/hcu4.c
View file

@ -58,12 +58,12 @@ int board_early_init_f (void)
* IRQ 17-24 RESERVED/UNUSED
* IRQ 31 (EXT IRQ 6) (unused)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
mtdcr(CPC0_ECR, 0x60606000);

42
board/netstal/hcu5/hcu5.c
View file

@ -129,29 +129,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */

12
board/netstal/mcu25/mcu25.c
View file

@ -64,12 +64,12 @@ int board_early_init_f (void)
* IRQ 17-24 RESERVED/UNUSED
* IRQ 31 (EXT IRQ 6) (unused)
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
mtdcr(CPC0_ECR, 0x60606000);

28
board/pcs440ep/pcs440ep.c
View file

@ -155,21 +155,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration

54
board/prodrive/alpr/alpr.c
View file

@ -60,36 +60,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic1pr, 0xfffffe03); /* per manual */
mtdcr (uic1tr, 0x01c00000); /* per manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (UIC1PR, 0xfffffe03); /* per manual */
mtdcr (UIC1TR, 0x01c00000); /* per manual */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000); /* */
mtdcr (uic0tr, 0x00000000); /* */
mtdcr (uic0vr, 0x00000001); /* */
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000); /* */
mtdcr (UIC0TR, 0x00000000); /* */
mtdcr (UIC0VR, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));

28
board/prodrive/p3p440/p3p440.c
View file

@ -101,21 +101,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}

14
board/quad100hd/quad100hd.c
View file

@ -40,13 +40,13 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* taken from PPCBoot */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7FFE); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */

24
board/sandburst/common/sb_common.c
View file

@ -266,11 +266,11 @@ long int fixed_sdram (void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@ -278,20 +278,20 @@ long int fixed_sdram (void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
mfsdram (SDRAM0_MCSTS, reg);
if (reg & 0x80000000)
break;
}

54
board/sandburst/karef/karef.c
View file

@ -212,36 +212,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000);
mtdcr (UIC0TR, 0x00000000);
mtdcr (UIC0VR, 0x00000001);
fpga_init();

54
board/sandburst/metrobox/metrobox.c
View file

@ -202,36 +202,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non- critical */
mtdcr (uic1pr, 0xfffffe03); /* polarity */
mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (UIC1ER, 0x00000000); /* disable all */
mtdcr (UIC1CR, 0x00000000); /* all non- critical */
mtdcr (UIC1PR, 0xfffffe03); /* polarity */
mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC1SR, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffc8ff); /* polarity */
mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (UIC2ER, 0x00000000); /* disable all */
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC2SR, 0xffffffff); /* clear all */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (uic3er, 0x00000000); /* disable all */
mtdcr (uic3cr, 0x00000000); /* all non-critical */
mtdcr (uic3pr, 0xffff83ff); /* polarity */
mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic3sr, 0xffffffff); /* clear all */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (UIC3ER, 0x00000000); /* disable all */
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
mtdcr (UIC3PR, 0xffff83ff); /* polarity */
mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (UIC3SR, 0xffffffff); /* clear all */
mtdcr (uic0sr, 0xfc000000); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000000); /* all non-critical */
mtdcr (uic0pr, 0xfc000000);
mtdcr (uic0tr, 0x00000000);
mtdcr (uic0vr, 0x00000001);
mtdcr (UIC0SR, 0xfc000000); /* clear all */
mtdcr (UIC0ER, 0x00000000); /* disable all */
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
mtdcr (UIC0PR, 0xfc000000);
mtdcr (UIC0TR, 0x00000000);
mtdcr (UIC0VR, 0x00000001);
fpga_init();

14
board/sbc405/sbc405.c
View file

@ -41,13 +41,13 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

40
board/sc3/sc3.c
View file

@ -294,22 +294,22 @@ int board_early_init_f (void)
writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
if (IS_CAMERON) {
sc3_cameron_init();
mtdcr (0x0B6, 0x18000000);
mtdcr (uicpr, 0xFFFFFFF0);
mtdcr (uictr, 0x10001030);
mtdcr (UIC0PR, 0xFFFFFFF0);
mtdcr (UIC0TR, 0x10001030);
} else {
mtdcr (0x0B6, 0x0000000);
mtdcr (uicpr, 0xFFFFFFE0);
mtdcr (uictr, 0x10000020);
mtdcr (UIC0PR, 0xFFFFFFE0);
mtdcr (UIC0TR, 0x10000020);
}
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
mtdcr (CPC0_ECR, 0x60606000);
@ -577,7 +577,7 @@ static int printSDRAMConfig(char reg, unsigned long cr)
}
#ifdef SC3_DEBUGOUT
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
#endif
phys_size_t initdram (int board_type)
@ -591,7 +591,7 @@ phys_size_t initdram (int board_type)
puts("\nSDRAM configuration:\n");
mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
ul1 = mfdcr(SDRAM0_CFGDATA);
if (!(ul1 & 0x80000000)) {
@ -604,7 +604,7 @@ phys_size_t initdram (int board_type)
mems += printSDRAMConfig (i, ul1);
}
mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
ul1 = mfdcr(SDRAM0_CFGDATA);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
@ -614,14 +614,14 @@ phys_size_t initdram (int board_type)
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
mtdcr (SDRAM0_CFGADDR, mem_rtr);
mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
ul1 = mfdcr(SDRAM0_CFGDATA);
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
mtdcr(SDRAM0_CFGADDR,mem_pmit);
mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
ul2=mfdcr(SDRAM0_CFGDATA);
mtdcr(SDRAM0_CFGADDR,mem_mcopt1);
mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
ul1=mfdcr(SDRAM0_CFGDATA);
if (ul1 & 0x20000000)
@ -658,7 +658,7 @@ phys_size_t initdram (int board_type)
else
puts(" -Memory lines only at write cycles active outputs\n");
mtdcr (SDRAM0_CFGADDR, mem_status);
mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
ul1 = mfdcr (SDRAM0_CFGDATA);
if (ul1 & 0x80000000)
puts(" -SDRAM Controller ready\n");
@ -670,19 +670,19 @@ phys_size_t initdram (int board_type)
return (mems * 1024 * 1024);
#else
mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
ul1 = mfdcr (SDRAM0_CFGDATA);
mems = printSDRAMConfig (0, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
ul1 = mfdcr (SDRAM0_CFGDATA);
mems += printSDRAMConfig (1, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (2, ul1);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
ul1 = mfdcr(SDRAM0_CFGDATA);
mems += printSDRAMConfig (3, ul1);

10
board/w7o/init.S
View file

@ -182,7 +182,7 @@ sdram_init:
* Disable memory controller to allow
* values to be changed.
*/
addi r3, 0, mem_mcopt1
addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0
ori r4, r4, 0x0
@ -192,7 +192,7 @@ sdram_init:
* Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
* All other banks are disabled.
*/
addi r3, 0, mem_mb0cf
addi r3, 0, SDRAM0_B0CR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
@ -222,7 +222,7 @@ sdram_init:
/*
* Set up SDTR1
*/
addi r3, 0, mem_sdtr1
addi r3, 0, SDRAM0_TR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
ori r4, r4, 0x400D
@ -231,7 +231,7 @@ sdram_init:
/*
* Set RTR
*/
addi r3, 0, mem_rtr
addi r3, 0, SDRAM0_RTR
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
mtdcr SDRAM0_CFGDATA, r4
@ -250,7 +250,7 @@ sdram_init:
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
addi r3, 0, mem_mcopt1
addi r3, 0, SDRAM0_CFG
mtdcr SDRAM0_CFGADDR, r3
addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */

36
board/w7o/w7o.c
View file

@ -64,16 +64,16 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#elif defined(CONFIG_W7OLMC)
/*
@ -95,16 +95,16 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#else /* Unknown */
# error "Unknown W7O board configuration"
@ -170,16 +170,16 @@ unsigned long get_dram_size (void)
int size = 0;
/* Get bank Size registers */
mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
regs[0] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
regs[1] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
regs[2] = mfdcr (SDRAM0_CFGDATA);
mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */
mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
regs[3] = mfdcr (SDRAM0_CFGDATA);
/* compute the size, add each bank if enabled */

54
board/xes/xpedite1000/xpedite1000.c
View file

@ -74,36 +74,36 @@ int board_early_init_f(void)
* UIC2 UIC1
* UIC3 UIC2
*/
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */
mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */
mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(UIC2ER, 0x00000000); /* disable all */
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */
mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */
mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC2SR, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(UIC3ER, 0x00000000); /* disable all */
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */
mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC3SR, 0xffffffff); /* clear all */
mtdcr(uic0sr, 0xfc000000); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000000); /* all non-critical */
mtdcr(uic0pr, 0xfc000000); /* */
mtdcr(uic0tr, 0x00000000); /* */
mtdcr(uic0vr, 0x00000001); /* */
mtdcr(UIC0SR, 0xfc000000); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000000); /* all non-critical */
mtdcr(UIC0PR, 0xfc000000); /* */
mtdcr(UIC0TR, 0x00000000); /* */
mtdcr(UIC0VR, 0x00000001); /* */
LED0_ON();

14
board/zeus/zeus.c
View file

@ -50,13 +50,13 @@ static u32 start_time;
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000);
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
mtdcr(uictr, 0x00000000); /* set int trigger levels */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000);
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
/*
* Configure CPC0_PCI to enable PerWE as output

78
common/cmd_reginfo.c
View file

@ -93,39 +93,39 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
mfdcr(UIC0SR),
mfdcr(UIC0ER),
mfdcr(UIC0CR),
mfdcr(UIC0PR),
mfdcr(UIC0TR),
mfdcr(UIC0MSR),
mfdcr(UIC0VR),
mfdcr(UIC0VCR));
puts ("\nMemory (SDRAM) Configuration\n"
"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
puts ("\n"
"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
printf ("\n\n"
"DMA Channels\n"
@ -180,27 +180,27 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined(CONFIG_405EP)
printf ("\n405EP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
mfdcr(UIC0SR),
mfdcr(UIC0ER),
mfdcr(UIC0CR),
mfdcr(UIC0PR),
mfdcr(UIC0TR),
mfdcr(UIC0MSR),
mfdcr(UIC0VR),
mfdcr(UIC0VCR));
puts ("\nMemory (SDRAM) Configuration\n"
"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
printf ("\n\n"
"DMA Channels\n"

27
cpu/ppc4xx/40x_spd_sdram.c
View file

@ -422,32 +422,31 @@ long int spd_sdram(int(read_spd)(uint addr))
* program all the registers.
* -------------------------------------------------------------------*/
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, 0 );
mtsdram(SDRAM0_CFG, 0);
#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_besra , sdram0_besr0 );
mtsdram0( mem_besrb , sdram0_besr1 );
mtsdram0( mem_ecccf , sdram0_ecccfg );
mtsdram0( mem_eccerr, sdram0_eccesr );
mtsdram(SDRAM0_BESR0, sdram0_besr0);
mtsdram(SDRAM0_BESR1, sdram0_besr1);
mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
#endif
mtsdram0( mem_rtr , sdram0_rtr );
mtsdram0( mem_pmit , sdram0_pmit );
mtsdram0( mem_mb0cf , sdram0_b0cr );
mtsdram0( mem_mb1cf , sdram0_b1cr );
mtsdram(SDRAM0_RTR, sdram0_rtr);
mtsdram(SDRAM0_PMIT, sdram0_pmit);
mtsdram(SDRAM0_B0CR, sdram0_b0cr);
mtsdram(SDRAM0_B1CR, sdram0_b1cr);
#ifndef CONFIG_405EP /* not on PPC405EP */
mtsdram0( mem_mb2cf , sdram0_b2cr );
mtsdram0( mem_mb3cf , sdram0_b3cr );
mtsdram(SDRAM0_B2CR, sdram0_b2cr);
mtsdram(SDRAM0_B3CR, sdram0_b3cr);
#endif
mtsdram0( mem_sdtr1 , sdram0_tr );
mtsdram(SDRAM0_TR, sdram0_tr);
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
mtsdram0(mem_mcopt1, sdram0_cfg);
mtsdram(SDRAM0_CFG, sdram0_cfg);
return (total_size);
}

44
cpu/ppc4xx/44x_spd_ddr.c
View file

@ -230,7 +230,7 @@ long int spd_sdram(void) {
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/
mtsdram(mem_clktr, 0x40000000);
mtsdram(SDRAM0_CLKTR, 0x40000000);
/*
* delay to ensure 200 usec has elapsed
@ -240,14 +240,14 @@ long int spd_sdram(void) {
/*
* enable the memory controller
*/
mfsdram(mem_cfg0, cfg0);
mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
mfsdram(SDRAM0_CFG0, cfg0);
mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
/*
* wait for SDRAM_CFG0_DC_EN to complete
*/
while (1) {
mfsdram(mem_mcsts, mcsts);
mfsdram(SDRAM0_MCSTS, mcsts);
if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
break;
}
@ -386,7 +386,7 @@ static void program_cfg0(unsigned long *dimm_populated,
/*
* get Memory Controller Options 0 data
*/
mfsdram(mem_cfg0, cfg0);
mfsdram(SDRAM0_CFG0, cfg0);
/*
* clear bits
@ -457,7 +457,7 @@ static void program_cfg0(unsigned long *dimm_populated,
* Note: DCEN must be enabled after all DDR SDRAM controller
* configuration registers get initialized.
*/
mtsdram(mem_cfg0, cfg0);
mtsdram(SDRAM0_CFG0, cfg0);
}
static void program_cfg1(unsigned long *dimm_populated,
@ -465,7 +465,7 @@ static void program_cfg1(unsigned long *dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long cfg1;
mfsdram(mem_cfg1, cfg1);
mfsdram(SDRAM0_CFG1, cfg1);
/*
* Self-refresh exit, disable PM
@ -475,7 +475,7 @@ static void program_cfg1(unsigned long *dimm_populated,
/*
* program Memory Controller Options 1
*/
mtsdram(mem_cfg1, cfg1);
mtsdram(SDRAM0_CFG1, cfg1);
}
static void program_rtr(unsigned long *dimm_populated,
@ -535,7 +535,7 @@ static void program_rtr(unsigned long *dimm_populated,
/*
* program Refresh Timer Register (SDRAM0_RTR)
*/
mtsdram(mem_rtr, sdram_rtr);
mtsdram(SDRAM0_RTR, sdram_rtr);
}
static void program_tr0(unsigned long *dimm_populated,
@ -576,7 +576,7 @@ static void program_tr0(unsigned long *dimm_populated,
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
mfsdram(mem_tr0, tr0);
mfsdram(SDRAM0_TR0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
@ -821,7 +821,7 @@ static void program_tr0(unsigned long *dimm_populated,
}
debug("tr0: %x\n", tr0);
mtsdram(mem_tr0, tr0);
mtsdram(SDRAM0_TR0, tr0);
}
static int short_mem_test(void)
@ -848,7 +848,7 @@ static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2));
mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */
membase = (unsigned long*)
@ -918,11 +918,11 @@ static void program_tr1(void)
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
mfsdram(mem_tr1, tr1);
mfsdram(SDRAM0_TR1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
mfsdram(mem_tr0, tr0);
mfsdram(SDRAM0_TR0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) {
tr1 |= SDRAM_TR1_RDSS_TR2;
@ -937,14 +937,14 @@ static void program_tr1(void)
/*
* save CFG0 ECC setting to a temporary variable and turn ECC off
*/
mfsdram(mem_cfg0, cfg0);
mfsdram(SDRAM0_CFG0, cfg0);
ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
/*
* get the delay line calibration register value
*/
mfsdram(mem_dlycal, dlycal);
mfsdram(SDRAM0_DLYCAL, dlycal);
dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
max_pass_length = 0;
@ -964,7 +964,7 @@ static void program_tr1(void)
/*
* Set the timing reg for the test.
*/
mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
if (fail_found == TRUE) {
@ -1018,7 +1018,7 @@ static void program_tr1(void)
/*
* restore the orignal ECC setting
*/
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
/*
* set the SDRAM TR1 RDCD value
@ -1056,7 +1056,7 @@ static void program_tr1(void)
/*
* program SDRAM Timing Register 1 TR1
*/
mtsdram(mem_tr1, tr1);
mtsdram(SDRAM0_TR1, tr1);
}
static unsigned long program_bxcr(unsigned long *dimm_populated,
@ -1086,7 +1086,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2));
mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0;
}
@ -1232,7 +1232,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |

60
cpu/ppc4xx/sdram.c
View file

@ -188,14 +188,14 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(SDRAM0_CFG, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
mtsdram(mem_mb0cf, mb0cf[i].reg);
mtsdram(mem_sdtr1, sdtr1);
mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
mtsdram(SDRAM0_TR, sdtr1);
mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@ -204,7 +204,7 @@ phys_size_t initdram(int board_type)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram(mem_mcopt1, 0x80800000);
mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
@ -216,9 +216,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
mtsdram(mem_mcopt1, 0x00000000);
mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000);
mtsdram(SDRAM0_CFG, 0x00000000);
mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
/*
@ -228,8 +228,8 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
mtsdram(SDRAM0_B1CR, 0);
mtsdram(SDRAM0_CFG, 0);
} else {
/*
* We have two identical banks, so the size
@ -315,7 +315,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i));
mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@ -383,31 +383,31 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
mtsdram(mem_cfg0, 0x00000000);
mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR);
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, mb0cf[i].reg);
mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR);
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
/*
* Enable the controller, then wait for DCEN to complete
*/
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
@ -416,7 +416,7 @@ phys_size_t initdram(int board_type)
* Optimize TR1 to current hardware environment
*/
sdram_tr1_set(0x00000000, &tr1_bank1);
mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
/*
@ -424,9 +424,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
mtsdram(mem_cfg0, 0);
mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
mtsdram(SDRAM0_CFG0, 0);
mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
/*
@ -436,9 +436,9 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
!= mb0cf[i].size) {
mtsdram(mem_cfg0, 0);
mtsdram(mem_b1cr, 0);
mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
mtsdram(SDRAM0_CFG0, 0);
mtsdram(SDRAM0_B1CR, 0);
mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
} else {
/*

28
cpu/ppc4xx/uic.c
View file

@ -109,7 +109,7 @@ void external_interrupt(struct pt_regs *regs)
/*
* Read masked interrupt status register to determine interrupt source
*/
uic_msr = mfdcr(uic0msr);
uic_msr = mfdcr(UIC0MSR);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
@ -129,7 +129,7 @@ void external_interrupt(struct pt_regs *regs)
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
mtdcr(uic0sr, (uic_msr & UICB0_ALL));
mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
@ -140,13 +140,13 @@ void external_interrupt(struct pt_regs *regs)
void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicsr, UIC_MASK(vec));
mtdcr(UIC0SR, UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1sr, UIC_MASK(vec));
mtdcr(UIC1SR, UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2sr, UIC_MASK(vec));
mtdcr(UIC2SR, UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3sr, UIC_MASK(vec));
mtdcr(UIC3SR, UIC_MASK(vec));
}
/*
@ -156,13 +156,13 @@ void pic_irq_enable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
debug("Install interrupt vector %d\n", vec);
}
@ -170,11 +170,11 @@ void pic_irq_enable(unsigned int vec)
void pic_irq_disable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
else if (vec >= 96)
mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
}

86
include/asm-ppc/ppc4xx-sdram.h
View file

@ -30,32 +30,27 @@
* SDRAM Controller
*/
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
* of course. sr, 2008-06-02
*/
#ifndef CONFIG_405EP
#define mem_besra 0x00 /* bus error syndrome reg a */
#define mem_besrsa 0x04 /* bus error syndrome reg set a */
#define mem_besrb 0x08 /* bus error syndrome reg b */
#define mem_besrsb 0x0c /* bus error syndrome reg set b */
#define mem_bear 0x10 /* bus error address reg */
#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
#define SDRAM0_BEAR 0x10 /* bus error address reg */
#endif
#define mem_mcopt1 0x20 /* memory controller options 1 */
#define mem_status 0x24 /* memory status */
#define mem_rtr 0x30 /* refresh timer reg */
#define mem_pmit 0x34 /* power management idle timer */
#define mem_mb0cf 0x40 /* memory bank 0 configuration */
#define mem_mb1cf 0x44 /* memory bank 1 configuration */
#define SDRAM0_CFG 0x20 /* memory controller options 1 */
#define SDRAM0_STATUS 0x24 /* memory status */
#define SDRAM0_RTR 0x30 /* refresh timer reg */
#define SDRAM0_PMIT 0x34 /* power management idle timer */
#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
#ifndef CONFIG_405EP
#define mem_mb2cf 0x48 /* memory bank 2 configuration */
#define mem_mb3cf 0x4c /* memory bank 3 configuration */
#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
#endif
#define mem_sdtr1 0x80 /* timing reg 1 */
#define SDRAM0_TR 0x80 /* timing reg 1 */
#ifndef CONFIG_405EP
#define mem_ecccf 0x94 /* ECC configuration */
#define mem_eccerr 0x98 /* ECC error status */
#define SDRAM0_ECCCFG 0x94 /* ECC configuration */
#define SDRAM0_ECCESR 0x98 /* ECC error status */
#endif
#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
@ -68,36 +63,25 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
* of course. sr, 2008-06-02
*/
#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
#define mem_bear 0x0010 /* bus error address reg */
#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
#define mem_slio 0x0018 /* ddr sdram slave interface options */
#define mem_cfg0 0x0020 /* ddr sdram options 0 */
#define mem_cfg1 0x0021 /* ddr sdram options 1 */
#define mem_devopt 0x0022 /* ddr sdram device options */
#define mem_mcsts 0x0024 /* memory controller status */
#define mem_rtr 0x0030 /* refresh timer register */
#define mem_pmit 0x0034 /* power management idle timer */
#define mem_uabba 0x0038 /* plb UABus base address */
#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
#define mem_tr0 0x0080 /* sdram timing register 0 */
#define mem_tr1 0x0081 /* sdram timing register 1 */
#define mem_clktr 0x0082 /* ddr clock timing register */
#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
#define mem_dlycal 0x0084 /* delay line calibration register */
#define mem_eccesr 0x0098 /* ECC error status */
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
#define SDRAM0_MCSTS 0x0024 /* memory controller status */
#define SDRAM0_RTR 0x0030 /* refresh timer register */
#define SDRAM0_PMIT 0x0034 /* power management idle timer */
#define SDRAM0_UABBA 0x0038 /* plb UABus base address */
#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
#define SDRAM0_ECCESR 0x0098 /* ECC error status */
/*
* Memory Controller Options 0

80
include/asm-ppc/ppc4xx-uic.h
View file

@ -1,7 +1,7 @@
/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* (C) Copyright 2008
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -43,7 +43,7 @@
#define UIC_MAX 1
#endif
#define IRQ_MAX UIC_MAX * 32
#define IRQ_MAX (UIC_MAX * 32)
/*
* UIC register
@ -74,53 +74,41 @@
#define UIC3_DCR_BASE 0xf0
#endif
#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
#define uicer uic0er
#define uiccr uic0cr
#define uicpr uic0pr
#define uictr uic0tr
#define uicmsr uic0msr
#define uicvr uic0vr
#define uicvcr uic0vcr
#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/*
* Now the interrupt vector definitions. They are different for most of

26
nand_spl/board/amcc/bamboo/sdram.c
View file

@ -31,7 +31,7 @@ static void wait_init_complete(void)
u32 val;
do {
mfsdram(mem_mcsts, val);
mfsdram(SDRAM0_MCSTS, val);
} while (!(val & 0x80000000));
}
@ -62,30 +62,30 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
mtsdram(mem_cfg0, 0x00000000);
mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x00082001);
mtsdram(mem_tr0, 0x41094012);
mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8ľs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
mtsdram(SDRAM0_B0CR, 0x00082001);
mtsdram(SDRAM0_TR0, 0x41094012);
mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8ｵs @ 133MHz PLB */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
/*
* Enable the controller, then wait for DCEN to complete
*/
mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
wait_init_complete();
return CONFIG_SYS_MBYTES_SDRAM << 20;