ppc4xx: Rework 4xx cache support
New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>utp
Stefan Roese
parent
06713773da
commit
9b94ac61d2
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@ -25,14 +25,38 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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START = start.o resetvec.o kgdb.o
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SOBJS = dcr.o
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COBJS = 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o \
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4xx_enet.o 4xx_pci.o 4xx_pcie.o 4xx_uart.o \
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bedbug_405.o commproc.o cpu.o cpu_init.o \
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fdt.o gpio.o i2c.o interrupts.o iop480_uart.o \
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miiphy.o ndfc.o sdram.o speed.o \
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tlb.o traps.o usb.o usb_ohci.o usbdev.o
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START := resetvec.o
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START += start.o
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SOBJS := cache.o
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SOBJS += dcr.o
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SOBJS += kgdb.o
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COBJS := 40x_spd_sdram.o
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COBJS += 44x_spd_ddr.o
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COBJS += 44x_spd_ddr2.o
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COBJS += 4xx_enet.o
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COBJS += 4xx_pci.o
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COBJS += 4xx_pcie.o
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COBJS += 4xx_uart.o
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COBJS += bedbug_405.o
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COBJS += commproc.o
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COBJS += cpu.o
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COBJS += cpu_init.o
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COBJS += fdt.o
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COBJS += gpio.o
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COBJS += i2c.o
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COBJS += interrupts.o
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COBJS += iop480_uart.o
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COBJS += miiphy.o
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COBJS += ndfc.o
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COBJS += sdram.o
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COBJS += speed.o
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COBJS += tlb.o
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COBJS += traps.o
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COBJS += usb.o
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COBJS += usb_ohci.o
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COBJS += usbdev.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -0,0 +1,233 @@
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/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <config.h>
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#include <config.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/*
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* Flush instruction cache.
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*/
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_GLOBAL(invalidate_icache)
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iccci r0,r0
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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sync /* additional sync needed on g4 */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*
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* clean_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(clean_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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blr
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/*
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* 40x cores have 8K or 16K dcache and 32 byte line size.
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* 44x has a 32K dcache and 32 byte line size.
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* 8xx has 1, 2, 4, 8K variants.
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* For now, cover the worst case of the 44x.
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* Must be called with external interrupts disabled.
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*/
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#define CACHE_NWAYS 64
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#define CACHE_NLINES 32
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_GLOBAL(flush_dcache)
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li r4,(2 * CACHE_NWAYS * CACHE_NLINES)
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mtctr r4
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lis r5,0
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1: lwz r3,0(r5) /* Load one word from every line */
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addi r5,r5,L1_CACHE_BYTES
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bdnz 1b
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sync
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blr
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_GLOBAL(invalidate_dcache)
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addi r6,0,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
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ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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..dcloop:
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dccci 0,r6 /* invalidate line */
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addi r6,r6,L1_CACHE_BYTES /* bump to next line */
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bdnz ..dcloop
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sync
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blr
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/*
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* Cache functions.
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*
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* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
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* although for some cache-ralated calls stubs have to be provided to satisfy
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* symbols resolution.
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* Icache-related functions are used in POST framework.
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*
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*/
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#ifdef CONFIG_440
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.globl dcache_disable
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.globl icache_disable
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.globl icache_enable
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dcache_disable:
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icache_disable:
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icache_enable:
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blr
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.globl dcache_status
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.globl icache_status
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dcache_status:
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icache_status:
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mr r3, 0
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blr
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#else /* CONFIG_440 */
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.globl icache_enable
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icache_enable:
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mflr r8
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0xc000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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.globl icache_status
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icache_status:
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mficcr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl dcache_enable
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dcache_enable:
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mflr r8
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mtdccr r3
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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.globl dcache_status
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dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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#endif /* CONFIG_440 */
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@ -56,21 +56,21 @@ kgdb_flush_cache_all:
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,CFG_CACHELINE_SIZE-1
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,CFG_CACHELINE_SHIFT
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CFG_CACHELINE_SIZE
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CFG_CACHELINE_SIZE
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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SYNC
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blr
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@ -1220,111 +1220,6 @@ mck_return:
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#endif /* CONFIG_440 */
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/*
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* Cache functions.
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*
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* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
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* although for some cache-ralated calls stubs have to be provided to satisfy
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* symbols resolution.
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* Icache-related functions are used in POST framework.
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*
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*/
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#ifdef CONFIG_440
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.globl dcache_disable
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.globl icache_disable
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.globl icache_enable
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dcache_disable:
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icache_disable:
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icache_enable:
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blr
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.globl dcache_status
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.globl icache_status
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dcache_status:
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icache_status:
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mr r3, 0
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blr
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#else
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flush_dcache:
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addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
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ori r9,r9,0x8000
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mfmsr r12 /* save msr */
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andc r9,r12,r9
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mtmsr r9 /* disable EE and CE */
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addi r10,r0,0x0001 /* enable data cache for unused memory */
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mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
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or r10,r10,r9 /* bit 31 in dccr */
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mtdccr r10
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/* do loop for # of congruence classes. */
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lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
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ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
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lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
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ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
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mtctr r10
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addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
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add r11,r10,r11 /* add to get to other side of cache line */
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..flush_dcache_loop:
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lwz r3,0(r10) /* least recently used side */
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lwz r3,0(r11) /* the other side */
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dccci r0,r11 /* invalidate both sides */
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addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
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addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
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bdnz ..flush_dcache_loop
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sync /* allow memory access to complete */
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mtdccr r9 /* restore dccr */
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mtmsr r12 /* restore msr */
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blr
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.globl icache_enable
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icache_enable:
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mflr r8
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0xc000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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.globl icache_status
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icache_status:
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mficcr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl dcache_enable
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dcache_enable:
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mflr r8
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mtdccr r3
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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.globl dcache_status
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dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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#endif
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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@ -1430,6 +1325,26 @@ ppcSync:
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*/
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.globl relocate_code
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relocate_code:
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#ifdef CONFIG_4xx_DCACHE
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/*
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* We need to flush the Init Data before the dcache will be
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* invalidated
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*/
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/* save regs */
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mr r9,r3
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mr r10,r4
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mr r11,r5
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mr r3,r4
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addi r4,r4,0x200 /* should be enough for init data */
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bl flush_dcache_range
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/* restore regs */
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mr r3,r9
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mr r4,r10
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mr r5,r11
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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@ -1457,7 +1372,7 @@ relocate_code:
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ori r4, r4, CFG_MONITOR_BASE@l
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lwz r5, GOT(__init_end)
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sub r5, r5, r4
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li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
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li r6, L1_CACHE_BYTES /* Cache Line Size */
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/*
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* Fix GOT pointer:
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@ -1777,23 +1692,6 @@ in32:
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lwz 3,0x0000(3)
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blr
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invalidate_icache:
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iccci r0,r0 /* for 405, iccci invalidates the */
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blr /* entire I cache */
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invalidate_dcache:
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addi r6,0,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
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ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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..dcloop:
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dccci 0,r6 /* invalidate line */
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addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
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bdnz ..dcloop
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blr
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/**************************************************************************/
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/* PPC405EP specific stuff */
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/**************************************************************************/
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||||
|
|
|
|||
|
|
@ -8,15 +8,24 @@
|
|||
#include <asm/processor.h>
|
||||
|
||||
/* bytes per L1 cache line */
|
||||
#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
|
||||
#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480))
|
||||
#if defined(CONFIG_PPC64BRIDGE)
|
||||
#define L1_CACHE_BYTES 128
|
||||
#define L1_CACHE_SHIFT 7
|
||||
#else
|
||||
#define L1_CACHE_BYTES 32
|
||||
#define L1_CACHE_SHIFT 5
|
||||
#endif /* PPC64 */
|
||||
#else
|
||||
#define L1_CACHE_BYTES 16
|
||||
#endif /* !8xx || 8260 */
|
||||
#define L1_CACHE_SHIFT 4
|
||||
#endif /* !(8xx || IOP480) */
|
||||
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
/*
|
||||
* For compatibility reasons support the CFG_CACHELINE_SIZE too
|
||||
*/
|
||||
#ifndef CFG_CACHELINE_SIZE
|
||||
#define CFG_CACHELINE_SIZE L1_CACHE_BYTES
|
||||
#endif
|
||||
|
||||
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
|
||||
#define L1_CACHE_PAGES 8
|
||||
|
|
@ -35,6 +44,8 @@
|
|||
extern void flush_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void clean_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void flush_dcache(void);
|
||||
extern void invalidate_dcache(void);
|
||||
#ifdef CFG_INIT_RAM_LOCK
|
||||
extern void unlock_ram_in_cache(void);
|
||||
#endif /* CFG_INIT_RAM_LOCK */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,12 @@
|
|||
#ifndef __PPC405_H__
|
||||
#define __PPC405_H__
|
||||
|
||||
#ifndef CONFIG_IOP480
|
||||
#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
|
||||
#else
|
||||
#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------- */
|
||||
/* Special Purpose Registers */
|
||||
/*--------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#ifndef __PPC440_H__
|
||||
#define __PPC440_H__
|
||||
|
||||
#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
|
||||
|
||||
/*--------------------------------------------------------------------- */
|
||||
/* Special Purpose Registers */
|
||||
/*--------------------------------------------------------------------- */
|
||||
|
|
@ -3282,8 +3284,4 @@ static inline void set_mcsr(u32 val)
|
|||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#define RESET_VECTOR 0xfffffffc
|
||||
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */
|
||||
/* cache line aligned data. */
|
||||
|
||||
#endif /* __PPC440_H__ */
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
|
||||
void flush_cache (ulong start_addr, ulong size)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue