mips: ath79: add AP143 reference board
This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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@ -3,6 +3,7 @@
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#
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dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
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dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
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dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
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targets += $(dtb-y)
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43
arch/mips/dts/ap143.dts
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43
arch/mips/dts/ap143.dts
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "qca953x.dtsi"
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/ {
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model = "AP143 Reference Board";
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compatible = "qca,ap143", "qca,qca953x";
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aliases {
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spi0 = &spi0;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&xtal {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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spi-max-frequency = <25000000>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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memory-map = <0x9f000000 0x00800000>;
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spi-max-frequency = <25000000>;
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reg = <0>;
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};
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};
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84
arch/mips/dts/qca953x.dtsi
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84
arch/mips/dts/qca953x.dtsi
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@ -0,0 +1,84 @@
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "qca,qca953x";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips24Kc";
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reg = <0>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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xtal: xtal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-output-names = "xtal";
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};
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};
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pinctrl {
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u-boot,dm-pre-reloc;
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compatible = "qca,qca953x-pinctrl";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x18040000 0x100>;
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};
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ahb {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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apb {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: uart@18020000 {
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compatible = "ns16550";
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reg = <0x18020000 0x20>;
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reg-shift = <2>;
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clock-frequency = <25000000>;
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interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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spi0: spi@1f000000 {
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compatible = "qca,ar7100-spi";
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reg = <0x1f000000 0x10>;
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interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -29,8 +29,13 @@ config TARGET_AP121
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bool "AP121 Reference Board"
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select SOC_AR933X
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config TARGET_AP143
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bool "AP143 Reference Board"
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select SOC_QCA953X
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endchoice
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source "board/qca/ap121/Kconfig"
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source "board/qca/ap143/Kconfig"
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endmenu
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12
board/qca/ap143/Kconfig
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12
board/qca/ap143/Kconfig
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if TARGET_AP143
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config SYS_VENDOR
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default "qca"
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config SYS_BOARD
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default "ap143"
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config SYS_CONFIG_NAME
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default "ap143"
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endif
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6
board/qca/ap143/MAINTAINERS
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6
board/qca/ap143/MAINTAINERS
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AP143 BOARD
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M: Wills Wang <wills.wang@live.com>
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S: Maintained
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F: board/qca/ap143/
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F: include/configs/ap143.h
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F: configs/ap143_defconfig
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5
board/qca/ap143/Makefile
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5
board/qca/ap143/Makefile
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ap143.o
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66
board/qca/ap143/ap143.c
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66
board/qca/ap143/ap143.c
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ddr.h>
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#include <debug_uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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void __iomem *regs;
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u32 val;
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regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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/*
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* GPIO9 as input, GPIO10 as output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OE);
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val |= QCA953X_GPIO(9);
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val &= ~QCA953X_GPIO(10);
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writel(val, regs + AR71XX_GPIO_REG_OE);
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/*
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* Enable GPIO10 as UART0_SOUT
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*/
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val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
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val &= ~QCA953X_GPIO_MUX_MASK(16);
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val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
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writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
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/*
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* Enable GPIO9 as UART0_SIN
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*/
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val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
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val &= ~QCA953X_GPIO_MUX_MASK(8);
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val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
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writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
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/*
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* Enable GPIO10 output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OUT);
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val |= QCA953X_GPIO(10);
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writel(val, regs + AR71XX_GPIO_REG_OUT);
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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ddr_init();
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return 0;
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}
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47
configs/ap143_defconfig
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47
configs/ap143_defconfig
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CONFIG_MIPS=y
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CONFIG_SYS_MALLOC_F_LEN=0x800
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_ARCH_ATH79=y
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CONFIG_TARGET_AP143=y
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CONFIG_DEFAULT_DEVICE_TREE="ap143"
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CONFIG_SYS_PROMPT="ap143 # "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_CRC32 is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_DATAFLASH=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PINCTRL=y
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CONFIG_QCA953X_PINCTRL=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0xb8020000
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CONFIG_DEBUG_UART_CLOCK=25000000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_SYS_NS16550=y
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CONFIG_ATH79_SPI=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_OF_LIBFDT=y
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90
include/configs/ap143.h
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90
include/configs/ap143.h
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_MHZ 325
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#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 0x8000
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#define CONFIG_SYS_ICACHE_SIZE 0x10000
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN 0x40000
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#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_LOAD_ADDR 0x81000000
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_CLK 25000000
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{9600, 19200, 38400, 57600, 115200}
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock2 " \
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"rootfstype=squashfs"
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#define CONFIG_BOOTCOMMAND "sf probe;" \
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"mtdparts default;" \
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"bootm 0x9f300000"
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#define CONFIG_LZMA
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#define MTDIDS_DEFAULT "nor0=spi-flash.0"
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#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
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"256k(u-boot),64k(u-boot-env)," \
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"2752k(rootfs),896k(uImage)," \
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"64k(NVRAM),64k(ART)"
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#define CONFIG_ENV_SPI_MAX_HZ 25000000
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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/*
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* Command
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*/
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#define CONFIG_CMD_MTDPARTS
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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/*
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* Diagnostics
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*/
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#define CONFIG_SYS_MEMTEST_END 0x83f00000
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#define CONFIG_CMD_MEMTEST
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#endif /* __CONFIG_H */
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