[FIX] Coding style cleanup
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@ -1,7 +1,7 @@
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/*
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/*
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* (C) Copyright 2007 Michal Simek
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* (C) Copyright 2007 Michal Simek
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*
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*
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* Michal SIMEK <monstr@monstr.eu>
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* Michal SIMEK <monstr@monstr.eu>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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* project.
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* project.
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@ -13,7 +13,7 @@
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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@ -35,34 +35,33 @@ typedef struct {
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u32 IsStarted; /* Device is currently started 0-no, 1-yes */
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u32 IsStarted; /* Device is currently started 0-no, 1-yes */
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XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
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XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
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XPacketFifoV100b SendFifo; /* FIFO used to send frames */
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XPacketFifoV100b SendFifo; /* FIFO used to send frames */
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} XEmac;
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} XEmac;
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
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#define XIIF_V123B_RESET_MASK 0xAUL
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#define XIIF_V123B_RESET_MASK 0xAUL
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
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/* This constant is used with the Reset Register */
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/* This constant is used with the Reset Register */
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#define XPF_RESET_FIFO_MASK 0x0000000A
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#define XPF_RESET_FIFO_MASK 0x0000000A
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#define XPF_COUNT_STATUS_REG_OFFSET 4UL
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#define XPF_COUNT_STATUS_REG_OFFSET 4UL
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/* * These constants are used with the Occupancy/Vacancy Count Register. This
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/* These constants are used with the Occupancy/Vacancy Count Register. This
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* register also contains FIFO status */
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* register also contains FIFO status */
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#define XPF_COUNT_MASK 0x0000FFFF
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#define XPF_COUNT_MASK 0x0000FFFF
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#define XPF_DEADLOCK_MASK 0x20000000
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#define XPF_DEADLOCK_MASK 0x20000000
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/* Offset of the MAC registers from the IPIF base address */
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/* Offset of the MAC registers from the IPIF base address */
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#define XEM_REG_OFFSET 0x1100UL
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#define XEM_REG_OFFSET 0x1100UL
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/*
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/*
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* Register offsets for the Ethernet MAC. Each register is 32 bits.
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* Register offsets for the Ethernet MAC. Each register is 32 bits.
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*/
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*/
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
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@ -78,31 +77,31 @@ typedef struct {
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* part of the IPIF IP Interrupt registers
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* part of the IPIF IP Interrupt registers
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*/
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*/
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/* A mask for all transmit interrupts, used in polled mode */
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/* A mask for all transmit interrupts, used in polled mode */
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
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XEM_EIR_XMIT_LFIFO_FULL_MASK)
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XEM_EIR_XMIT_LFIFO_FULL_MASK)
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
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* overrun */
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* overrun */
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
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* underrun */
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* underrun */
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
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* overrun */
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* overrun */
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
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* underrun */
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* underrun */
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
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* overrun */
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* overrun */
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
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* underrun */
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* underrun */
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
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* received */
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* received */
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/*
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/*
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* addr */
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* addr */
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/* Transmit Status Register (TSR) */
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/* Transmit Status Register (TSR) */
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
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@ -29,7 +29,7 @@
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#ifdef XILINX_EMACLITE_BASEADDR
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#ifdef XILINX_EMACLITE_BASEADDR
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//#define DEBUG
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#undef DEBUG
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#define ENET_MAX_MTU PKTSIZE
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#define ENET_MAX_MTU PKTSIZE
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#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
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#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
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@ -310,7 +310,7 @@ int eth_rx (void)
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BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
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BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
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Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
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Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
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#ifdef DEBUG
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#ifdef DEBUG
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// printf ("Testing data at address 0x%x\n", BaseAddress);
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printf ("Testing data at address 0x%x\n", BaseAddress);
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#endif
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#endif
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if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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#ifdef XILINX_EMACLITE_RX_PING_PONG
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#ifdef XILINX_EMACLITE_RX_PING_PONG
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@ -319,7 +319,7 @@ int eth_rx (void)
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} else {
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} else {
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#ifndef XILINX_EMACLITE_RX_PING_PONG
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#ifndef XILINX_EMACLITE_RX_PING_PONG
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#ifdef DEBUG
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#ifdef DEBUG
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// printf ("No data was available - address 0x%x\n", BaseAddress);
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printf ("No data was available - address 0x%x\n", BaseAddress);
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#endif
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#endif
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return 0;
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return 0;
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#else
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#else
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if ((Register & XEL_RSR_RECV_DONE_MASK) !=
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if ((Register & XEL_RSR_RECV_DONE_MASK) !=
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XEL_RSR_RECV_DONE_MASK) {
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XEL_RSR_RECV_DONE_MASK) {
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#ifdef DEBUG
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#ifdef DEBUG
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// printf ("No data was available - address 0x%x\n",
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printf ("No data was available - address 0x%x\n",
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// BaseAddress);
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BaseAddress);
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#endif
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#endif
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return 0;
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return 0;
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}
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}
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@ -87,7 +87,7 @@
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* 0x11FB_F000 CFG_MONITOR_BASE
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* 0x11FB_F000 CFG_MONITOR_BASE
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* MONITOR_CODE 256kB Env
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* MONITOR_CODE 256kB Env
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* 0x13FF_F000 CFG_GBL_DATA_OFFSET
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* 0x13FF_F000 CFG_GBL_DATA_OFFSET
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* GLOBAL_DATA 4kB bd, gd
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* GLOBAL_DATA 4kB bd, gd
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* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
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* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
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*/
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*/
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/* global pointer */
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/* global pointer */
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#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
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#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
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/* start of global data */
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/* start of global data */
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#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
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#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
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/* monitor code */
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/* monitor code */
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#define SIZE 0x40000
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#define SIZE 0x40000
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#define CONFIG_BOOTDELAY 30
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#define CONFIG_BOOTDELAY 30
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_HOSTNAME "ml401"
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#define CONFIG_HOSTNAME "ml401"
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_SERVERIP 192.168.0.5
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#define CONFIG_SERVERIP 192.168.0.5
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
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#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
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/* architecture dependent code */
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/* architecture dependent code */
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