x86: Convert to use driver model pci on queensbay/crownbay
Move to driver model pci for Intel queensbay/crownbay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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@ -6,4 +6,3 @@
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obj-y += fsp_configs.o
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obj-y += tnc.o topcliff.o
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obj-$(CONFIG_PCI) += tnc_pci.o
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@ -25,7 +25,6 @@ static void unprotect_spi_flash(void)
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int arch_cpu_init(void)
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{
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struct pci_controller *hose;
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int ret;
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post_code(POST_CPU_INIT);
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@ -37,10 +36,6 @@ int arch_cpu_init(void)
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if (ret)
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return ret;
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ret = pci_early_init_hose(&hose);
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if (ret)
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return ret;
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unprotect_spi_flash();
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return 0;
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@ -1,46 +0,0 @@
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/fsp/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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@ -90,8 +90,12 @@
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,pci";
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compatible = "pci-x86";
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device_type = "pci";
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pcie@17,0 {
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#address-cells = <3>;
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@ -17,6 +17,7 @@ CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_OF_CONTROL=y
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CONFIG_CPU=y
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CONFIG_DM_PCI=y
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CONFIG_SPI_FLASH=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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