x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>utp
Bin Meng
parent
87077e97d1
commit
a2e3b05e16
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@ -79,4 +79,8 @@ config FSP_USE_UPD
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bool
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default n
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config FSP_BROKEN_HOB
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bool
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default y
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endif
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@ -5,6 +5,7 @@
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dtb-y += bayleybay.dtb \
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chromebook_link.dtb \
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chromebox_panther.dtb \
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cougarcanyon2.dtb \
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crownbay.dtb \
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efi.dtb \
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galileo.dtb \
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@ -0,0 +1,104 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Intel Cougar Canyon 2";
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compatible = "intel,cougarcanyon2", "intel,chiefriver";
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aliases {
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spi0 = &spi0;
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};
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = "/serial";
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};
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microcode {
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update@0 {
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#include "microcode/m12306a2_00000008.dtsi"
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};
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update@1 {
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#include "microcode/m12306a4_00000007.dtsi"
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};
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update@2 {
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#include "microcode/m12306a5_00000007.dtsi"
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};
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update@3 {
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#include "microcode/m12306a8_00000010.dtsi"
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};
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update@4 {
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#include "microcode/m12306a9_0000001b.dtsi"
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};
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};
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fsp {
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compatible = "intel,ivybridge-fsp";
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fsp,enable-ht;
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-x86";
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
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0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,bd82x6x";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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spi0: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9-spi";
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spi-flash@0 {
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reg = <0>;
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compatible = "winbond,w25q64bv", "spi-flash";
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memory-map = <0xff800000 0x00800000>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x10>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x30 0x10>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x10>;
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bank-name = "C";
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};
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};
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};
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};
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@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
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4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
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PCIe and some other sensor interfaces.
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config TARGET_COUGARCANYON2
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bool "Cougar Canyon 2"
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help
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This is the Intel Cougar Canyon 2 Customer Reference Board. It
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is built on the Chief River platform with Intel Ivybridge Processor
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and Panther Point chipset. The board has 4GB RAM, with some other
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peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
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config TARGET_CROWNBAY
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bool "Crown Bay"
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help
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@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
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endchoice
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source "board/intel/bayleybay/Kconfig"
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source "board/intel/cougarcanyon2/Kconfig"
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source "board/intel/crownbay/Kconfig"
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source "board/intel/galileo/Kconfig"
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source "board/intel/minnowmax/Kconfig"
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@ -0,0 +1,25 @@
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if TARGET_COUGARCANYON2
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config SYS_BOARD
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default "cougarcanyon2"
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config SYS_VENDOR
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default "intel"
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config SYS_SOC
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default "ivybridge"
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config SYS_CONFIG_NAME
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default "cougarcanyon2"
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config SYS_TEXT_BASE
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default 0xffe00000
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select X86_RESET_VECTOR
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select HAVE_FSP
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select BOARD_ROMSIZE_KB_2048
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endif
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@ -0,0 +1,6 @@
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INTEL COUGAR CANYON 2 BOARD
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M: Bin Meng <bmeng.cn@gmail.com>
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S: Maintained
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F: board/intel/cougarcanyon2/
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F: include/configs/cougarcanyon2.h
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F: configs/cougarcanyon2_defconfig
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@ -0,0 +1,7 @@
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#
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# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cougarcanyon2.o start.o
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@ -0,0 +1,58 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <pci.h>
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#include <smsc_sio1007.h>
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#include <asm/ibmpc.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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#define SIO1007_RUNTIME_IOPORT 0x180
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int board_early_init_f(void)
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{
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struct udevice *pch;
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int ret;
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ret = uclass_first_device(UCLASS_PCH, &pch);
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if (ret)
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return ret;
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if (!pch)
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return -ENODEV;
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/* Initialize LPC interface to turn on superio chipset decode range */
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dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
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dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
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dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
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(SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
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dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
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SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
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/* Enable legacy serial port at 0x3f8 */
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sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
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/* Enable SIO1007 runtime I/O port at 0x180 */
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sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
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/*
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* On Cougar Canyon 2 board, the RS232 transiver connected to serial
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* port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
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* Set the pin value to 1 to enable the RS232 transiver.
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*/
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sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
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GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
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sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
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return 0;
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}
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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return;
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}
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@ -0,0 +1,9 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.globl early_board_init
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early_board_init:
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jmp early_board_init_ret
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@ -0,0 +1,20 @@
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CONFIG_X86=y
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CONFIG_VENDOR_INTEL=y
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CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
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CONFIG_TARGET_COUGARCANYON2=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_OF_CONTROL=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_PCI=y
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CONFIG_DM_RTC=y
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CONFIG_SYS_NS16550=y
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CONFIG_ICH_SPI=y
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CONFIG_TIMER=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -133,6 +133,27 @@ $ make all
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---
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Intel Cougar Canyon 2 specific instructions for bare mode:
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This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
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with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
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website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
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time of writing) in the board directory and rename it to fsp.bin.
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Now build U-Boot and obtain u-boot.rom
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$ make cougarcanyon2_defconfig
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$ make all
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The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
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the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
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and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
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flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
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this image to the SPI-0 flash according to the board manual just once and we are
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all set. For programming U-Boot we just need to program SPI-1 flash.
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---
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Intel Minnowboard Max instructions for bare mode:
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This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_MONITOR_LEN (2 << 20)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SMSC_SIO1007
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#define CONFIG_PCI_PNP
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
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"stdout=serial,vga\0" \
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"stderr=serial,vga\0"
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#define CONFIG_SCSI_DEV_LIST \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
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/* Environment configuration */
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_OFFSET 0x5ff000
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/* Video is not supported for now */
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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#endif /* __CONFIG_H */
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