ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x
Signed-off-by: Alison Wang <b18965@freescale.com>utp
Alison Wang
jason
parent
c6d8863015
commit
a4110eecf2
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@ -3,7 +3,7 @@
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -31,19 +31,20 @@
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#include <netdev.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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gptmr->pre = 10;
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gptmr->cnt = 1;
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out_be16(&gptmr->pre, 10);
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out_be16(&gptmr->cnt, 1);
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/* enable watchdog, set timeout to 0 and wait */
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gptmr->mode = GPT_TMS_SGPIO;
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gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
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out_8(&gptmr->mode, GPT_TMS_SGPIO);
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out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
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/* we don't return! */
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return 1;
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@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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int checkcpu(void)
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{
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volatile siu_t *siu = (siu_t *) MMAP_SIU;
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siu_t *siu = (siu_t *) MMAP_SIU;
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u16 id = 0;
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puts("CPU: ");
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switch ((siu->jtagid & 0x000FF000) >> 12) {
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switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
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case 0x0C:
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id = 5485;
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break;
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@ -111,18 +112,18 @@ int checkcpu(void)
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/* Called by macro WATCHDOG_RESET */
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void hw_watchdog_reset(void)
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{
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volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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gptmr->ocpw = 0xa5;
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out_8(&gptmr->ocpw, 0xa5);
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}
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int watchdog_disable(void)
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{
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volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
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gptmr->mode = 0;
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gptmr->ctrl = 0;
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out_8(&gptmr->mode, 0);
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out_8(&gptmr->ctrl, 0);
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puts("WATCHDOG:disabled\n");
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@ -131,14 +132,13 @@ int watchdog_disable(void)
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int watchdog_init(void)
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{
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gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
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out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
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out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
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gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
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gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
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gptmr->mode = GPT_TMS_SGPIO;
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gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
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out_8(&gptmr->mode, GPT_TMS_SGPIO);
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out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
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puts("WATCHDOG:enabled\n");
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return (0);
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@ -3,7 +3,7 @@
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -28,6 +28,7 @@
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#include <common.h>
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#include <MCD_dma.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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@ -44,58 +45,59 @@
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*/
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void cpu_init_f(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
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xlbarb->adrto = 0x2000;
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xlbarb->datto = 0x2500;
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xlbarb->busto = 0x3000;
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out_be32(&xlbarb->adrto, 0x2000);
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out_be32(&xlbarb->datto, 0x2500);
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out_be32(&xlbarb->busto, 0x3000);
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xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;
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out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
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/* Master Priority Enable */
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xlbarb->prien = 0xff;
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xlbarb->pri = 0;
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out_be32(&xlbarb->prien, 0xff);
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out_be32(&xlbarb->pri, 0);
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
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out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
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out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
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out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
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out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
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out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
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out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
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out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
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out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
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out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
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out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
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out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA;
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out_be16(&gpio->par_feci2cirq,
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GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
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#endif
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icache_enable();
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@ -115,44 +117,44 @@ int cpu_init_r(void)
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void uart_port_conf(int port)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
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/* Setup Ports: */
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switch (port) {
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case 0:
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gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
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out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
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break;
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case 1:
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gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
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out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
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break;
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case 2:
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gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
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out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
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break;
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case 3:
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gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
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out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
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break;
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}
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*pscsicr &= 0xF8;
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clrbits_8(pscsicr, 0x07);
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
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if (setclear) {
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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gpio->par_feci2cirq |= 0xF000;
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setbits_be16(&gpio->par_feci2cirq, 0xf000);
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else
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gpio->par_feci2cirq |= 0x0FC0;
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setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
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} else {
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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gpio->par_feci2cirq &= 0x0FFF;
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clrbits_be16(&gpio->par_feci2cirq, 0xf000);
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else
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gpio->par_feci2cirq &= 0xF03F;
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clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
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}
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return 0;
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}
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@ -1,6 +1,6 @@
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/*
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -25,14 +25,15 @@
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/* CPU specific interrupt routine */
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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int interrupt_init(void)
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{
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volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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/* Make sure all interrupts are disabled */
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intp->imrh0 |= 0xFFFFFFFF;
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intp->imrl0 |= 0xFFFFFFFF;
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setbits_be32(&intp->imrh0, 0xffffffff);
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setbits_be32(&intp->imrl0, 0xffffffff);
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enable_interrupts();
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@ -42,9 +43,9 @@ int interrupt_init(void)
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#if defined(CONFIG_SLTTMR)
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void dtimer_intr_setup(void)
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{
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volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
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intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
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intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
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out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
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clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
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}
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
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void pci_mcf547x_8x_init(struct pci_controller *hose)
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{
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volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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pci_t *pci = (pci_t *) MMAP_PCI;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Port configuration */
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gpio->par_pcibg =
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GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
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GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
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GPIO_PAR_PCIBG_PCIBG4(3);
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gpio->par_pcibr =
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GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
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GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
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GPIO_PAR_PCIBR_PCIBR4(3);
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out_be16(&gpio->par_pcibg,
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GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
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GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
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GPIO_PAR_PCIBG_PCIBG4(3));
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out_be16(&gpio->par_pcibr,
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GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
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GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
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GPIO_PAR_PCIBR_PCIBR4(3));
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/* Assert reset bit */
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pci->gscr |= PCI_GSCR_PR;
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setbits_be32(&pci->gscr, PCI_GSCR_PR);
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pci->tcr1 = PCI_TCR1_P;
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out_be32(&pci->tcr1, PCI_TCR1_P);
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/* Initiator windows */
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pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
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pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
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pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
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out_be32(&pci->iw0btar,
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CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
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out_be32(&pci->iw1btar,
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CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
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out_be32(&pci->iw2btar,
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CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
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pci->iwcr =
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PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
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PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
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out_be32(&pci->iwcr,
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PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
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PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
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pci->icr = 0;
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out_be32(&pci->icr, 0);
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/* Enable bus master and mem access */
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pci->scr = PCI_SCR_B | PCI_SCR_M;
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out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
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/* Cache line size and master latency */
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pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
|
||||
pci->cr2 = 0;
|
||||
out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
|
||||
out_be32(&pci->cr2, 0);
|
||||
|
||||
#ifdef CONFIG_SYS_PCI_BAR0
|
||||
pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
|
||||
pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
|
||||
out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
|
||||
out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_PCI_BAR1
|
||||
pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
|
||||
pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
|
||||
out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
|
||||
out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
|
||||
#endif
|
||||
|
||||
/* Deassert reset bit */
|
||||
pci->gscr &= ~PCI_GSCR_PR;
|
||||
clrbits_be32(&pci->gscr, PCI_GSCR_PR);
|
||||
udelay(1000);
|
||||
|
||||
/* Enable PCI bus master support */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#include <asm/timer.h>
|
||||
#include <asm/immap.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -42,31 +43,32 @@ extern void dtimer_intr_setup(void);
|
|||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
|
||||
slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
|
||||
u32 now, freq;
|
||||
|
||||
/* 1 us period */
|
||||
freq = CONFIG_SYS_TIMER_PRESCALER;
|
||||
|
||||
timerp->cr = 0; /* Disable */
|
||||
timerp->tcnt = usec * freq;
|
||||
timerp->cr = SLT_CR_TEN;
|
||||
/* Disable */
|
||||
out_be32(&timerp->cr, 0);
|
||||
out_be32(&timerp->tcnt, usec * freq);
|
||||
out_be32(&timerp->cr, SLT_CR_TEN);
|
||||
|
||||
now = timerp->cnt;
|
||||
now = in_be32(&timerp->cnt);
|
||||
while (now != 0)
|
||||
now = timerp->cnt;
|
||||
now = in_be32(&timerp->cnt);
|
||||
|
||||
timerp->sr |= SLT_SR_ST;
|
||||
timerp->cr = 0;
|
||||
setbits_be32(&timerp->sr, SLT_SR_ST);
|
||||
out_be32(&timerp->cr, 0);
|
||||
}
|
||||
|
||||
void dtimer_interrupt(void *not_used)
|
||||
{
|
||||
volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
|
||||
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
|
||||
|
||||
/* check for timer interrupt asserted */
|
||||
if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
|
||||
timerp->sr |= SLT_SR_ST;
|
||||
setbits_be32(&timerp->sr, SLT_SR_ST);
|
||||
timestamp++;
|
||||
return;
|
||||
}
|
||||
|
|
@ -74,25 +76,27 @@ void dtimer_interrupt(void *not_used)
|
|||
|
||||
int timer_init(void)
|
||||
{
|
||||
volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
|
||||
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
|
||||
|
||||
timestamp = 0;
|
||||
|
||||
timerp->cr = 0; /* disable timer */
|
||||
timerp->tcnt = 0;
|
||||
timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */
|
||||
/* disable timer */
|
||||
out_be32(&timerp->cr, 0);
|
||||
out_be32(&timerp->tcnt, 0);
|
||||
/* clear status */
|
||||
out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
|
||||
|
||||
/* initialize and enable timer interrupt */
|
||||
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
|
||||
|
||||
/* Interrupt every ms */
|
||||
timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
|
||||
out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
|
||||
|
||||
dtimer_intr_setup();
|
||||
|
||||
/* set a period of 1us, set timer mode to restart and
|
||||
enable timer and interrupt */
|
||||
timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
|
||||
out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -28,6 +28,7 @@
|
|||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/immap.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -40,14 +41,14 @@ int checkboard(void)
|
|||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
siu_t *siu = (siu_t *) (MMAP_SIU);
|
||||
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
#ifdef CONFIG_SYS_DRAMSZ1
|
||||
u32 temp;
|
||||
#endif
|
||||
|
||||
siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
|
||||
out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
|
||||
|
||||
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
|
|
@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
|
|||
break;
|
||||
}
|
||||
i--;
|
||||
siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
|
||||
|
||||
#ifdef CONFIG_SYS_DRAMSZ1
|
||||
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
|
||||
|
|
@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
|
|||
}
|
||||
i--;
|
||||
dramsize += temp;
|
||||
siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
|
||||
out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
|
||||
#endif
|
||||
|
||||
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
|
||||
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
|
||||
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
|
||||
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
|
||||
|
||||
sdram->mode = CONFIG_SYS_SDRAM_MODE;
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
|
||||
out_be32(&sdram->ctrl,
|
||||
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
|
||||
|
||||
udelay(100);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
|
@ -28,6 +28,7 @@
|
|||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/immap.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -40,14 +41,14 @@ int checkboard(void)
|
|||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
|
||||
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
|
||||
siu_t *siu = (siu_t *) (MMAP_SIU);
|
||||
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
|
||||
u32 dramsize, i;
|
||||
#ifdef CONFIG_SYS_DRAMSZ1
|
||||
u32 temp;
|
||||
#endif
|
||||
|
||||
siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
|
||||
out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
|
||||
|
||||
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
|
||||
for (i = 0x13; i < 0x20; i++) {
|
||||
|
|
@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
|
|||
break;
|
||||
}
|
||||
i--;
|
||||
siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
|
||||
out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
|
||||
|
||||
#ifdef CONFIG_SYS_DRAMSZ1
|
||||
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
|
||||
|
|
@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
|
|||
}
|
||||
i--;
|
||||
dramsize += temp;
|
||||
siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
|
||||
out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
|
||||
#endif
|
||||
|
||||
sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
|
||||
sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
|
||||
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
|
||||
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
|
||||
/* Issue LEMR */
|
||||
sdram->mode = CONFIG_SYS_SDRAM_EMOD;
|
||||
sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* Issue PALL */
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
|
||||
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
|
||||
|
||||
sdram->mode = CONFIG_SYS_SDRAM_MODE;
|
||||
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
|
||||
|
||||
sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
|
||||
out_be32(&sdram->ctrl,
|
||||
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
|
||||
|
||||
udelay(100);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue