arc: add AXS101 board support
AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>utp
Alexey Brodkin
Tom Rini
parent
66712b8b46
commit
a7069ddfa9
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += axs101.o
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obj-$(CONFIG_CMD_NAND) += nand.o
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_mmc_init(bd_t *bis)
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{
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struct dwmci_host *host = NULL;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return 1;
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}
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memset(host, 0, sizeof(struct dwmci_host));
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host->name = "Synopsys Mobile storage";
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host->ioaddr = (void *)ARC_DWMMC_BASE;
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host->buswidth = 4;
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host->dev_index = 0;
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host->bus_hz = 25000000;
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add_dwmci(host, 52000000, 400000);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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if (designware_initialize(0, ARC_DWGMAC_BASE, 0,
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PHY_INTERFACE_MODE_RGMII) >= 0)
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return 1;
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return 0;
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}
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@ -0,0 +1,226 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <malloc.h>
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#include <nand.h>
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#include <asm/io.h>
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#define BUS_WIDTH 8 /* AXI data bus width in bytes */
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/* DMA buffer descriptor bits & masks */
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#define BD_STAT_OWN (1 << 31)
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#define BD_STAT_BD_FIRST (1 << 3)
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#define BD_STAT_BD_LAST (1 << 2)
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#define BD_SIZES_BUFFER1_MASK 0xfff
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#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
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/* Controller command flags */
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#define B_WFR (1 << 19) /* 1b - Wait for ready */
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#define B_LC (1 << 18) /* 1b - Last cycle */
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#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
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/* NAND cycle types */
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#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
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#define B_CT_COMMAND (0x1 << 16) /* Command operation */
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#define B_CT_WRITE (0x2 << 16) /* Write operation */
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#define B_CT_READ (0x3 << 16) /* Write operation */
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enum nand_isr_t {
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NAND_ISR_DATAREQUIRED = 0,
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NAND_ISR_TXUNDERFLOW,
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NAND_ISR_TXOVERFLOW,
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NAND_ISR_DATAAVAILABLE,
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NAND_ISR_RXUNDERFLOW,
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NAND_ISR_RXOVERFLOW,
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NAND_ISR_TXDMACOMPLETE,
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NAND_ISR_RXDMACOMPLETE,
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NAND_ISR_DESCRIPTORUNAVAILABLE,
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NAND_ISR_CMDDONE,
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NAND_ISR_CMDAVAILABLE,
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NAND_ISR_CMDERROR,
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NAND_ISR_DATATRANSFEROVER,
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NAND_ISR_NONE
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};
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enum nand_regs_t {
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AC_FIFO = 0, /* address and command fifo */
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IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
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INT_STATUS = 0x118, /* interrupt status register */
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INT_CLR_STATUS = 0x120, /* interrupt clear status register */
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};
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struct nand_bd {
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uint32_t status; /* DES0 */
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uint32_t sizes; /* DES1 */
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uint32_t buffer_ptr0; /* DES2 */
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uint32_t buffer_ptr1; /* DES3 */
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};
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#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r)
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#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r)
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static struct nand_bd *bd; /* DMA buffer descriptors */
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/**
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* axs101_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static uint32_t nand_flag_is_set(uint32_t flag)
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{
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uint32_t reg = NAND_REG_READ(INT_STATUS);
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if (reg & (1 << NAND_ISR_CMDERROR))
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return 0;
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if (reg & (1 << flag)) {
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NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
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return 1;
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}
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return 0;
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}
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/**
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* axs101_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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struct bounce_buffer bbstate;
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bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
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/* Setup buffer descriptor */
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writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
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writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
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writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
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writel(0, &bd->buffer_ptr1);
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/* Issue "write" command */
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NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
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/* Wait for NAND command and DMA to complete */
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
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;
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bounce_buffer_stop(&bbstate);
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}
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/**
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* axs101_nand_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store data
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* @len: number of bytes to read
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*/
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static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct bounce_buffer bbstate;
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bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
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/* Setup buffer descriptor */
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writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
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writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
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writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
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writel(0, &bd->buffer_ptr1);
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/* Issue "read" command */
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NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
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/* Wait for NAND command and DMA to complete */
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
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;
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bounce_buffer_stop(&bbstate);
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}
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/**
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* axs101_nand_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*/
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static u_char axs101_nand_read_byte(struct mtd_info *mtd)
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{
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u8 byte;
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axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
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return byte;
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}
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/**
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* axs101_nand_read_word - read one word from the chip
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* @mtd: MTD device structure
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*/
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static u16 axs101_nand_read_word(struct mtd_info *mtd)
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{
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u16 word;
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axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
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return word;
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}
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/**
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* axs101_nand_hwcontrol - NAND control functions wrapper.
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* @mtd: MTD device structure
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* @cmd: Command
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*/
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static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
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unsigned int ctrl)
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{
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if (cmd == NAND_CMD_NONE)
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return;
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cmd = cmd & 0xff;
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switch (ctrl & (NAND_ALE | NAND_CLE)) {
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/* Address */
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case NAND_ALE:
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cmd |= B_CT_ADDRESS;
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break;
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/* Command */
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case NAND_CLE:
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cmd |= B_CT_COMMAND | B_WFR;
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break;
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default:
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debug("%s: unknown ctrl %#x\n", __func__, ctrl);
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}
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NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
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sizeof(struct nand_bd));
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/* Set buffer descriptor address in IDMAC */
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NAND_REG_WRITE(IDMAC_BDADDR, bd);
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = axs101_nand_hwcontrol;
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nand->read_byte = axs101_nand_read_byte;
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nand->read_word = axs101_nand_read_word;
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nand->write_buf = axs101_nand_write_buf;
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nand->read_buf = axs101_nand_read_buf;
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return 0;
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}
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@ -1230,6 +1230,7 @@ Active sparc leon3 - gaisler -
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Active sparc leon3 - gaisler - gr_xc3s_1500 - -
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Active sparc leon3 - gaisler - grsim - -
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Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
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Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
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Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
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Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
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Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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@ -0,0 +1,181 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_AXS101_H_
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#define _CONFIG_AXS101_H_
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/*
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* CPU configuration
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*/
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#define CONFIG_ARC700
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#define CONFIG_ARC_MMU_VER 3
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_CLK_FREQ 750000000
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#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
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/* dwgmac doesn't work with D$ enabled now */
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Board configuration
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*/
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
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#define CONFIG_ARCH_EARLY_INIT_R
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#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
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#define ARC_APB_PERIPHERAL_BASE 0xF0000000
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#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
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#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
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/*
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* Memory configuration
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*/
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#define CONFIG_SYS_TEXT_BASE 0x81000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
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#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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/*
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* NAND Flash configuration
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*/
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/*
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* UART configuration
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*
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* CONFIG_CONS_INDEX = 1 - Debug UART
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* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
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*/
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#define CONFIG_CONS_INDEX 4
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#if (CONFIG_CONS_INDEX == 1)
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/* Debug UART */
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# define CONFIG_SYS_NS16550_CLK 33333000
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#else
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/* FPGA UARTs use different clock */
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# define CONFIG_SYS_NS16550_CLK 33333333
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#endif
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#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
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#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
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#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
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#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_BAUDRATE 115200
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_DW_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_ENV_EEPROM_BUS 2
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_I2C_BASE 0xE001D000
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#define CONFIG_SYS_I2C_BASE1 0xE001E000
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#define CONFIG_SYS_I2C_BASE2 0xE001F000
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#define CONFIG_SYS_I2C_BUS_MAX 3
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#define IC_CLK 50
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32
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/*
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* SD/MMC configuration
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*/
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DWMMC
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#define CONFIG_DOS_PARTITION
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/*
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* Ethernet PHY configuration
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*/
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#define CONFIG_PHYLIB
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#define CONFIG_MII
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#define CONFIG_PHY_GIGE
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/*
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* Ethernet configuration
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*/
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#define CONFIG_DESIGNWARE_ETH
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#define CONFIG_DW_AUTONEG
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#define CONFIG_DW_SEARCH_PHY
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#define CONFIG_NET_MULTI
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/*
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* Command line configuration
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RARP
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#define CONFIG_OF_LIBFDT
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 16
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
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#define CONFIG_ENV_OFFSET 0
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/*
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* Environment configuration
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*/
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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||||
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||||
/*
|
||||
* Console configuration
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "axs# "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/*
|
||||
* Misc utility configuration
|
||||
*/
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
#endif /* _CONFIG_AXS101_H_ */
|
||||
Loading…
Reference in New Issue