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arm: socfpga: Add socfpga_spim_enable() to reset_manager.c 

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
utp
Stefan Roese 2014-11-07 13:50:30 +01:00 committed by Marek Vasut
parent d2bb937db9
commit a877bec3ec
3 changed files with 18 additions and 0 deletions
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6
arch/arm/cpu/armv7/socfpga/misc.c
View File

@ -202,6 +202,12 @@ int arch_early_init_r(void)
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
#ifdef CONFIG_DESIGNWARE_SPI
/* Get Designware SPI controller out of reset */
socfpga_spim_enable();
#endif
return 0;
}

9
arch/arm/cpu/armv7/socfpga/reset_manager.c
View File

@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
#endif
}
}
/* SPI Master enable (its held in reset by the preloader) */
void socfpga_spim_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
}

3
arch/arm/include/asm/arch-socfpga/reset_manager.h
View File

@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
void socfpga_spim_enable(void);
struct socfpga_reset_manager {
u32 status;
@ -35,5 +36,7 @@ struct socfpga_reset_manager {
#define RSTMGR_PERMODRST_EMAC0_LSB 0
#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
#define RSTMGR_PERMODRST_SPIM0_LSB 18
#define RSTMGR_PERMODRST_SPIM1_LSB 19
#endif /* _RESET_MANAGER_H_ */