dm: spi: Convert Freescale DSPI driver to driver model
Move the Freescale DSPI driver over to driver model. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>utp
Haikun.Wang@freescale.com
Simon Glass
parent
863b4e1b9d
commit
a891937110
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@ -50,3 +50,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
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obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
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obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
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obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
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obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
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@ -0,0 +1,737 @@
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* Chao Fu (B44548@freescale.com)
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* Haikun Wang (B53464@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dm.h>
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#include <errno.h>
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <fdtdec.h>
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#ifndef CONFIG_M68K
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#include <asm/arch/clock.h>
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#endif
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#include <fsl_dspi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* fsl_dspi_platdata flags */
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#define DSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
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/* idle data value */
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#define DSPI_IDLE_VAL 0x0
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/* max chipselect signals number */
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#define FSL_DSPI_MAX_CHIPSELECT 6
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/* default SCK frequency, unit: HZ */
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#define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
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/* tx/rx data wait timeout value, unit: us */
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#define DSPI_TXRX_WAIT_TIMEOUT 1000000
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/* CTAR register pre-configure value */
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#define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
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DSPI_CTAR_PCSSCK_1CLK | \
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DSPI_CTAR_PASC(0) | \
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DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | \
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DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(0))
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/* CTAR register pre-configure mask */
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#define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
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DSPI_CTAR_PCSSCK(3) | \
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DSPI_CTAR_PASC(3) | \
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DSPI_CTAR_PDT(3) | \
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DSPI_CTAR_CSSCK(15) | \
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DSPI_CTAR_ASC(15) | \
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DSPI_CTAR_DT(15))
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/**
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* struct fsl_dspi_platdata - platform data for Freescale DSPI
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*
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* @flags: Flags for DSPI DSPI_FLAG_...
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* @speed_hz: Default SCK frequency
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* @num_chipselect: Number of DSPI chipselect signals
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* @regs_addr: Base address of DSPI registers
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*/
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struct fsl_dspi_platdata {
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uint flags;
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uint speed_hz;
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uint num_chipselect;
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fdt_addr_t regs_addr;
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};
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/**
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* struct fsl_dspi_priv - private data for Freescale DSPI
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*
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* @flags: Flags for DSPI DSPI_FLAG_...
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* @mode: SPI mode to use for slave device (see SPI mode flags)
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* @mcr_val: MCR register configure value
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* @bus_clk: DSPI input clk frequency
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* @speed_hz: Default SCK frequency
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* @charbit: How many bits in every transfer
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* @num_chipselect: Number of DSPI chipselect signals
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* @ctar_val: CTAR register configure value of per chipselect slave device
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* @regs: Point to DSPI register structure for I/O access
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*/
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struct fsl_dspi_priv {
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uint flags;
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uint mode;
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uint mcr_val;
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uint bus_clk;
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uint speed_hz;
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uint charbit;
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uint num_chipselect;
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uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
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struct dspi *regs;
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};
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#ifndef CONFIG_DM_SPI
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struct fsl_dspi {
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struct spi_slave slave;
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struct fsl_dspi_priv priv;
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};
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#endif
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__weak void cpu_dspi_port_conf(void)
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{
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}
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__weak int cpu_dspi_claim_bus(uint bus, uint cs)
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{
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return 0;
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}
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__weak void cpu_dspi_release_bus(uint bus, uint cs)
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{
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}
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static uint dspi_read32(uint flags, uint *addr)
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{
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return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
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in_be32(addr) : in_le32(addr);
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}
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static void dspi_write32(uint flags, uint *addr, uint val)
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{
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flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
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out_be32(addr, val) : out_le32(addr, val);
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}
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static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
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{
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uint mcr_val;
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mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
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if (halt)
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mcr_val |= DSPI_MCR_HALT;
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else
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mcr_val &= ~DSPI_MCR_HALT;
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dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
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}
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static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
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{
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/* halt DSPI module */
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dspi_halt(priv, 1);
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dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
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/* resume module */
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dspi_halt(priv, 0);
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priv->mcr_val = cfg_val;
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}
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static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
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uint cs, uint state)
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{
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uint mcr_val;
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dspi_halt(priv, 1);
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mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
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if (state & SPI_CS_HIGH)
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/* CSx inactive state is low */
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mcr_val &= ~DSPI_MCR_PCSIS(cs);
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else
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/* CSx inactive state is high */
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mcr_val |= DSPI_MCR_PCSIS(cs);
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dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
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dspi_halt(priv, 0);
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}
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static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
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uint cs, uint mode)
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{
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uint bus_setup;
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bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
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bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
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bus_setup |= priv->ctar_val[cs];
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bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
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if (mode & SPI_CPOL)
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bus_setup |= DSPI_CTAR_CPOL;
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if (mode & SPI_CPHA)
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bus_setup |= DSPI_CTAR_CPHA;
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if (mode & SPI_LSB_FIRST)
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bus_setup |= DSPI_CTAR_LSBFE;
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dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
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priv->charbit =
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((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
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DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
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return 0;
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}
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static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
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{
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uint mcr_val;
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dspi_halt(priv, 1);
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mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
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/* flush RX and TX FIFO */
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mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
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dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
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dspi_halt(priv, 0);
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}
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static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
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{
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int timeout = DSPI_TXRX_WAIT_TIMEOUT;
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/* wait for empty entries in TXFIFO or timeout */
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while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
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timeout--)
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udelay(1);
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if (timeout >= 0)
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dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
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else
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debug("dspi_tx: waiting timeout!\n");
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}
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static u16 dspi_rx(struct fsl_dspi_priv *priv)
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{
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int timeout = DSPI_TXRX_WAIT_TIMEOUT;
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/* wait for valid entries in RXFIFO or timeout */
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while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
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timeout--)
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udelay(1);
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if (timeout >= 0)
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return (u16)DSPI_RFR_RXDATA(
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dspi_read32(priv->flags, &priv->regs->rfr));
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else {
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debug("dspi_rx: waiting timeout!\n");
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return (u16)(~0);
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}
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}
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static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
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u8 *spi_rd = NULL, *spi_wr = NULL;
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static u32 ctrl;
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uint len = bitlen >> 3;
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if (priv->charbit == 16) {
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bitlen >>= 1;
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spi_wr16 = (u16 *)dout;
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spi_rd16 = (u16 *)din;
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} else {
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spi_wr = (u8 *)dout;
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spi_rd = (u8 *)din;
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}
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if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
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ctrl |= DSPI_TFR_CONT;
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ctrl = ctrl & DSPI_TFR_CONT;
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ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
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if (len > 1) {
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int tmp_len = len - 1;
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while (tmp_len--) {
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if (dout != NULL) {
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if (priv->charbit == 16)
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dspi_tx(priv, ctrl, *spi_wr16++);
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else
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dspi_tx(priv, ctrl, *spi_wr++);
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dspi_rx(priv);
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}
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if (din != NULL) {
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dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
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if (priv->charbit == 16)
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*spi_rd16++ = dspi_rx(priv);
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else
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*spi_rd++ = dspi_rx(priv);
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}
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}
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len = 1; /* remaining byte */
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}
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if ((flags & SPI_XFER_END) == SPI_XFER_END)
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ctrl &= ~DSPI_TFR_CONT;
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if (len) {
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if (dout != NULL) {
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if (priv->charbit == 16)
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dspi_tx(priv, ctrl, *spi_wr16);
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else
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dspi_tx(priv, ctrl, *spi_wr);
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dspi_rx(priv);
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}
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if (din != NULL) {
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dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
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if (priv->charbit == 16)
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*spi_rd16 = dspi_rx(priv);
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else
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*spi_rd = dspi_rx(priv);
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}
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} else {
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/* dummy read */
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dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
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dspi_rx(priv);
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}
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return 0;
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}
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/**
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* Calculate the divide value between input clk frequency and expected SCK frequency
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* Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
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* Dbr: use default value 0
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*
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* @pbr: return Baud Rate Prescaler value
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* @br: return Baud Rate Scaler value
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* @speed_hz: expected SCK frequency
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* @clkrate: input clk frequency
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*/
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static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
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int speed_hz, uint clkrate)
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{
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/* Valid baud rate pre-scaler values */
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int pbr_tbl[4] = {2, 3, 5, 7};
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int brs[16] = {2, 4, 6, 8,
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768};
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int temp, i = 0, j = 0;
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temp = clkrate / speed_hz;
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for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
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for (j = 0; j < ARRAY_SIZE(brs); j++) {
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if (pbr_tbl[i] * brs[j] >= temp) {
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*pbr = i;
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*br = j;
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return 0;
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}
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}
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debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
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debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
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*pbr = ARRAY_SIZE(pbr_tbl) - 1;
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*br = ARRAY_SIZE(brs) - 1;
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return -EINVAL;
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}
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static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
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{
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int ret;
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uint bus_setup;
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int best_i, best_j, bus_clk;
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bus_clk = priv->bus_clk;
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debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
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speed, bus_clk);
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bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
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bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
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ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
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if (ret) {
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speed = priv->speed_hz;
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debug("DSPI set_speed use default SCK rate %u.\n", speed);
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fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
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}
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bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
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dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
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priv->speed_hz = speed;
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return 0;
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}
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#ifndef CONFIG_DM_SPI
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void spi_init(void)
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{
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/* Nothing to do */
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}
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void spi_init_f(void)
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{
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/* Nothing to do */
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}
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void spi_init_r(void)
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{
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/* Nothing to do */
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
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return 1;
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else
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return 0;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct fsl_dspi *dspi;
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uint mcr_cfg_val;
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dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
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if (!dspi)
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return NULL;
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cpu_dspi_port_conf();
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#ifdef CONFIG_SYS_FSL_DSPI_BE
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dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
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#endif
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dspi->priv.regs = (struct dspi *)MMAP_DSPI;
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#ifdef CONFIG_M68K
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dspi->priv.bus_clk = gd->bus_clk;
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#else
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dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
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#endif
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dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
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/* default: all CS signals inactive state is high */
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mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
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for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
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dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
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#ifdef CONFIG_SYS_DSPI_CTAR0
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if (FSL_DSPI_MAX_CHIPSELECT > 0)
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dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
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#endif
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#ifdef CONFIG_SYS_DSPI_CTAR1
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if (FSL_DSPI_MAX_CHIPSELECT > 1)
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dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR2
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 2)
|
||||
dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR3
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 3)
|
||||
dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR4
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 4)
|
||||
dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR5
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 5)
|
||||
dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR6
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 6)
|
||||
dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DSPI_CTAR7
|
||||
if (FSL_DSPI_MAX_CHIPSELECT > 7)
|
||||
dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
|
||||
#endif
|
||||
|
||||
fsl_dspi_cfg_speed(&dspi->priv, max_hz);
|
||||
|
||||
/* configure transfer mode */
|
||||
fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
|
||||
|
||||
/* configure active state of CSX */
|
||||
fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
|
||||
|
||||
return &dspi->slave;
|
||||
}
|
||||
|
||||
void spi_free_slave(struct spi_slave *slave)
|
||||
{
|
||||
free(slave);
|
||||
}
|
||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
uint sr_val;
|
||||
struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
|
||||
|
||||
cpu_dspi_claim_bus(slave->bus, slave->cs);
|
||||
|
||||
fsl_dspi_clr_fifo(&dspi->priv);
|
||||
|
||||
/* check module TX and RX status */
|
||||
sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
|
||||
if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
|
||||
debug("DSPI RX/TX not ready!\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
|
||||
|
||||
dspi_halt(&dspi->priv, 1);
|
||||
cpu_dspi_release_bus(slave->bus.slave->cs);
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
||||
void *din, unsigned long flags)
|
||||
{
|
||||
struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
|
||||
return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
|
||||
}
|
||||
#else
|
||||
static int fsl_dspi_child_pre_probe(struct udevice *dev)
|
||||
{
|
||||
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
||||
struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
|
||||
|
||||
if (slave_plat->cs >= priv->num_chipselect) {
|
||||
debug("DSPI invalid chipselect number %d(max %d)!\n",
|
||||
slave_plat->cs, priv->num_chipselect - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
|
||||
|
||||
debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
|
||||
slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_dspi_probe(struct udevice *bus)
|
||||
{
|
||||
struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
|
||||
struct fsl_dspi_priv *priv = dev_get_priv(bus);
|
||||
struct dm_spi_bus *dm_spi_bus;
|
||||
uint mcr_cfg_val;
|
||||
|
||||
dm_spi_bus = bus->uclass_priv;
|
||||
|
||||
/* cpu speical pin muxing configure */
|
||||
cpu_dspi_port_conf();
|
||||
|
||||
/* get input clk frequency */
|
||||
priv->regs = (struct dspi *)plat->regs_addr;
|
||||
priv->flags = plat->flags;
|
||||
#ifdef CONFIG_M68K
|
||||
priv->bus_clk = gd->bus_clk;
|
||||
#else
|
||||
priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
|
||||
#endif
|
||||
priv->num_chipselect = plat->num_chipselect;
|
||||
priv->speed_hz = plat->speed_hz;
|
||||
/* frame data length in bits, default 8bits */
|
||||
priv->charbit = 8;
|
||||
|
||||
dm_spi_bus->max_hz = plat->speed_hz;
|
||||
|
||||
/* default: all CS signals inactive state is high */
|
||||
mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
|
||||
DSPI_MCR_CRXF | DSPI_MCR_CTXF;
|
||||
fsl_dspi_init_mcr(priv, mcr_cfg_val);
|
||||
|
||||
debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_dspi_claim_bus(struct udevice *dev)
|
||||
{
|
||||
uint sr_val;
|
||||
struct fsl_dspi_priv *priv;
|
||||
struct udevice *bus = dev->parent;
|
||||
struct dm_spi_slave_platdata *slave_plat =
|
||||
dev_get_parent_platdata(dev);
|
||||
|
||||
priv = dev_get_priv(bus);
|
||||
|
||||
/* processor special prepartion work */
|
||||
cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
|
||||
|
||||
/* configure transfer mode */
|
||||
fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
|
||||
|
||||
/* configure active state of CSX */
|
||||
fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
|
||||
priv->mode);
|
||||
|
||||
fsl_dspi_clr_fifo(priv);
|
||||
|
||||
/* check module TX and RX status */
|
||||
sr_val = dspi_read32(priv->flags, &priv->regs->sr);
|
||||
if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
|
||||
debug("DSPI RX/TX not ready!\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_dspi_release_bus(struct udevice *dev)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct fsl_dspi_priv *priv = dev_get_priv(bus);
|
||||
struct dm_spi_slave_platdata *slave_plat =
|
||||
dev_get_parent_platdata(dev);
|
||||
|
||||
/* halt module */
|
||||
dspi_halt(priv, 1);
|
||||
|
||||
/* processor special release work */
|
||||
cpu_dspi_release_bus(bus->seq, slave_plat->cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function doesn't do anything except help with debugging
|
||||
*/
|
||||
static int fsl_dspi_bind(struct udevice *bus)
|
||||
{
|
||||
debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
fdt_addr_t addr;
|
||||
struct fsl_dspi_platdata *plat = bus->platdata;
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = bus->of_offset;
|
||||
|
||||
if (fdtdec_get_bool(blob, node, "big-endian"))
|
||||
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
|
||||
|
||||
plat->num_chipselect =
|
||||
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
|
||||
|
||||
addr = fdtdec_get_addr(blob, node, "reg");
|
||||
if (addr == FDT_ADDR_T_NONE) {
|
||||
debug("DSPI: Can't get base address or size\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
plat->regs_addr = addr;
|
||||
|
||||
plat->speed_hz = fdtdec_get_int(blob,
|
||||
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
|
||||
|
||||
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
|
||||
plat->regs_addr, plat->speed_hz,
|
||||
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
|
||||
plat->num_chipselect);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
struct fsl_dspi_priv *priv;
|
||||
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
||||
struct udevice *bus;
|
||||
|
||||
bus = dev->parent;
|
||||
priv = dev_get_priv(bus);
|
||||
|
||||
return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
|
||||
}
|
||||
|
||||
static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
|
||||
{
|
||||
struct fsl_dspi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
return fsl_dspi_cfg_speed(priv, speed);
|
||||
}
|
||||
|
||||
static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
|
||||
{
|
||||
struct fsl_dspi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
debug("DSPI set_mode: mode 0x%x.\n", mode);
|
||||
|
||||
/*
|
||||
* We store some chipselect special configure value in priv->ctar_val,
|
||||
* and we can't get the correct chipselect number here,
|
||||
* so just store mode value.
|
||||
* Do really configuration when claim_bus.
|
||||
*/
|
||||
priv->mode = mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops fsl_dspi_ops = {
|
||||
.claim_bus = fsl_dspi_claim_bus,
|
||||
.release_bus = fsl_dspi_release_bus,
|
||||
.xfer = fsl_dspi_xfer,
|
||||
.set_speed = fsl_dspi_set_speed,
|
||||
.set_mode = fsl_dspi_set_mode,
|
||||
};
|
||||
|
||||
static const struct udevice_id fsl_dspi_ids[] = {
|
||||
{ .compatible = "fsl,vf610-dspi" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(fsl_dspi) = {
|
||||
.name = "fsl_dspi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = fsl_dspi_ids,
|
||||
.ops = &fsl_dspi_ops,
|
||||
.ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
|
||||
.priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
|
||||
.probe = fsl_dspi_probe,
|
||||
.child_pre_probe = fsl_dspi_child_pre_probe,
|
||||
.bind = fsl_dspi_bind,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Freescale DSPI Module Defines
|
||||
*
|
||||
* Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
* Chao Fu (B44548@freesacle.com)
|
||||
* Haikun Wang (B53464@freescale.com)
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DSPI_H_
|
||||
#define _FSL_DSPI_H_
|
||||
|
||||
/* DMA Serial Peripheral Interface (DSPI) */
|
||||
struct dspi {
|
||||
u32 mcr; /* 0x00 */
|
||||
u32 resv0; /* 0x04 */
|
||||
u32 tcr; /* 0x08 */
|
||||
u32 ctar[8]; /* 0x0C - 0x28 */
|
||||
u32 sr; /* 0x2C */
|
||||
u32 irsr; /* 0x30 */
|
||||
u32 tfr; /* 0x34 - PUSHR */
|
||||
u32 rfr; /* 0x38 - POPR */
|
||||
#ifdef CONFIG_MCF547x_8x
|
||||
u32 tfdr[4]; /* 0x3C */
|
||||
u8 resv2[0x30]; /* 0x40 */
|
||||
u32 rfdr[4]; /* 0x7C */
|
||||
#else
|
||||
u32 tfdr[16]; /* 0x3C */
|
||||
u32 rfdr[16]; /* 0x7C */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Module configuration */
|
||||
#define DSPI_MCR_MSTR 0x80000000
|
||||
#define DSPI_MCR_CSCK 0x40000000
|
||||
#define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28)
|
||||
#define DSPI_MCR_FRZ 0x08000000
|
||||
#define DSPI_MCR_MTFE 0x04000000
|
||||
#define DSPI_MCR_PCSSE 0x02000000
|
||||
#define DSPI_MCR_ROOE 0x01000000
|
||||
#define DSPI_MCR_PCSIS(x) (1 << (16 + (x)))
|
||||
#define DSPI_MCR_PCSIS_MASK (0xff << 16)
|
||||
#define DSPI_MCR_CSIS7 0x00800000
|
||||
#define DSPI_MCR_CSIS6 0x00400000
|
||||
#define DSPI_MCR_CSIS5 0x00200000
|
||||
#define DSPI_MCR_CSIS4 0x00100000
|
||||
#define DSPI_MCR_CSIS3 0x00080000
|
||||
#define DSPI_MCR_CSIS2 0x00040000
|
||||
#define DSPI_MCR_CSIS1 0x00020000
|
||||
#define DSPI_MCR_CSIS0 0x00010000
|
||||
#define DSPI_MCR_DOZE 0x00008000
|
||||
#define DSPI_MCR_MDIS 0x00004000
|
||||
#define DSPI_MCR_DTXF 0x00002000
|
||||
#define DSPI_MCR_DRXF 0x00001000
|
||||
#define DSPI_MCR_CTXF 0x00000800
|
||||
#define DSPI_MCR_CRXF 0x00000400
|
||||
#define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8)
|
||||
#define DSPI_MCR_FCPCS 0x00000001
|
||||
#define DSPI_MCR_PES 0x00000001
|
||||
#define DSPI_MCR_HALT 0x00000001
|
||||
|
||||
/* Transfer count */
|
||||
#define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16)
|
||||
|
||||
/* Clock and transfer attributes */
|
||||
#define DSPI_CTAR(x) (0x0c + (x * 4))
|
||||
#define DSPI_CTAR_DBR 0x80000000
|
||||
#define DSPI_CTAR_TRSZ(x) (((x) & 0x0F) << 27)
|
||||
#define DSPI_CTAR_CPOL 0x04000000
|
||||
#define DSPI_CTAR_CPHA 0x02000000
|
||||
#define DSPI_CTAR_LSBFE 0x01000000
|
||||
#define DSPI_CTAR_PCSSCK(x) (((x) & 0x03) << 22)
|
||||
#define DSPI_CTAR_PCSSCK_7CLK 0x00A00000
|
||||
#define DSPI_CTAR_PCSSCK_5CLK 0x00800000
|
||||
#define DSPI_CTAR_PCSSCK_3CLK 0x00400000
|
||||
#define DSPI_CTAR_PCSSCK_1CLK 0x00000000
|
||||
#define DSPI_CTAR_PASC(x) (((x) & 0x03) << 20)
|
||||
#define DSPI_CTAR_PASC_7CLK 0x00300000
|
||||
#define DSPI_CTAR_PASC_5CLK 0x00200000
|
||||
#define DSPI_CTAR_PASC_3CLK 0x00100000
|
||||
#define DSPI_CTAR_PASC_1CLK 0x00000000
|
||||
#define DSPI_CTAR_PDT(x) (((x) & 0x03) << 18)
|
||||
#define DSPI_CTAR_PDT_7CLK 0x000A0000
|
||||
#define DSPI_CTAR_PDT_5CLK 0x00080000
|
||||
#define DSPI_CTAR_PDT_3CLK 0x00040000
|
||||
#define DSPI_CTAR_PDT_1CLK 0x00000000
|
||||
#define DSPI_CTAR_PBR(x) (((x) & 0x03) << 16)
|
||||
#define DSPI_CTAR_PBR_7CLK 0x00030000
|
||||
#define DSPI_CTAR_PBR_5CLK 0x00020000
|
||||
#define DSPI_CTAR_PBR_3CLK 0x00010000
|
||||
#define DSPI_CTAR_PBR_1CLK 0x00000000
|
||||
#define DSPI_CTAR_CSSCK(x) (((x) & 0x0F) << 12)
|
||||
#define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8)
|
||||
#define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4)
|
||||
#define DSPI_CTAR_BR(x) ((x) & 0x0F)
|
||||
|
||||
/* Status */
|
||||
#define DSPI_SR_TCF 0x80000000
|
||||
#define DSPI_SR_TXRXS 0x40000000
|
||||
#define DSPI_SR_EOQF 0x10000000
|
||||
#define DSPI_SR_TFUF 0x08000000
|
||||
#define DSPI_SR_TFFF 0x02000000
|
||||
#define DSPI_SR_RFOF 0x00080000
|
||||
#define DSPI_SR_RFDF 0x00020000
|
||||
#define DSPI_SR_TXCTR(x) (((x) & 0x0000F000) >> 12)
|
||||
#define DSPI_SR_TXPTR(x) (((x) & 0x00000F00) >> 8)
|
||||
#define DSPI_SR_RXCTR(x) (((x) & 0x000000F0) >> 4)
|
||||
#define DSPI_SR_RXPTR(x) ((x) & 0x0000000F)
|
||||
|
||||
/* DMA/interrupt request selct and enable */
|
||||
#define DSPI_IRSR_TCFE 0x80000000
|
||||
#define DSPI_IRSR_EOQFE 0x10000000
|
||||
#define DSPI_IRSR_TFUFE 0x08000000
|
||||
#define DSPI_IRSR_TFFFE 0x02000000
|
||||
#define DSPI_IRSR_TFFFS 0x01000000
|
||||
#define DSPI_IRSR_RFOFE 0x00080000
|
||||
#define DSPI_IRSR_RFDFE 0x00020000
|
||||
#define DSPI_IRSR_RFDFS 0x00010000
|
||||
|
||||
/* Transfer control - 32-bit access */
|
||||
#define DSPI_TFR_PCS(x) (((1 << x) & 0x0000003f) << 16)
|
||||
#define DSPI_TFR_CONT 0x80000000
|
||||
#define DSPI_TFR_CTAS(x) (((x) & 0x07) << 28)
|
||||
#define DSPI_TFR_EOQ 0x08000000
|
||||
#define DSPI_TFR_CTCNT 0x04000000
|
||||
#define DSPI_TFR_CS7 0x00800000
|
||||
#define DSPI_TFR_CS6 0x00400000
|
||||
#define DSPI_TFR_CS5 0x00200000
|
||||
#define DSPI_TFR_CS4 0x00100000
|
||||
#define DSPI_TFR_CS3 0x00080000
|
||||
#define DSPI_TFR_CS2 0x00040000
|
||||
#define DSPI_TFR_CS1 0x00020000
|
||||
#define DSPI_TFR_CS0 0x00010000
|
||||
|
||||
/* Transfer Fifo */
|
||||
#define DSPI_TFR_TXDATA(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/* Bit definitions and macros for DRFR */
|
||||
#define DSPI_RFR_RXDATA(x) ((x) & 0x0000FFFF)
|
||||
|
||||
/* Bit definitions and macros for DTFDR group */
|
||||
#define DSPI_TFDR_TXDATA(x) ((x) & 0x0000FFFF)
|
||||
#define DSPI_TFDR_TXCMD(x) (((x) & 0x0000FFFF) << 16)
|
||||
|
||||
/* Bit definitions and macros for DRFDR group */
|
||||
#define DSPI_RFDR_RXDATA(x) ((x) & 0x0000FFFF)
|
||||
|
||||
#endif /* _FSL_DSPI_H_ */
|
||||
Loading…
Reference in New Issue