Move machine specific code to board at s3c64xx (v2)
Move machine specific code to smdk6400. Some board use OneNAND instead of NAND. Some register MP0_CS_CFG[5:0] are controled by both h/w and s/w. So it's better to use macro instead of hard-coded value. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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@ -104,6 +104,13 @@ lowlevel_init:
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bl nand_asm_init
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#endif
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/* Memory subsystem address 0x7e00f120 */
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ldr r0, =ELFIN_MEM_SYS_CFG
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/* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
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mov r1, #S3C64XX_MEM_SYS_CFG_NAND
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str r1, [r0]
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bl mem_ctrl_asm_init
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/* Wakeup support. Don't know if it's going to be used, untested. */
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@ -28,13 +28,6 @@
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.globl mem_ctrl_asm_init
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mem_ctrl_asm_init:
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/* Memory subsystem address 0x7e00f120 */
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ldr r0, =ELFIN_MEM_SYS_CFG
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/* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
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mov r1, #0xd
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str r1, [r0]
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/* DMC1 base address 0x7e001000 */
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ldr r0, =ELFIN_DMC1_BASE
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@ -380,6 +380,11 @@
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*/
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#define ELFIN_MEM_SYS_CFG 0x7e00f120
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#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
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#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
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#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
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#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
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#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
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#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
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