Merge branch 'master' of git://git.denx.de/u-boot-ti
Tom Rini
commit
ab77f24119
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@ -76,13 +76,13 @@ static void configure_mr(int nr, u32 cs)
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}
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/*
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* Configure EMIF4D5 registers and MR registers
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* Configure EMIF4D5 registers and MR registers For details about these magic
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* values please see the EMIF registers section of the TRM.
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*/
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void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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{
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writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
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writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
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writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
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writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
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writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
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@ -106,10 +106,45 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
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}
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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/*
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* Sequence to ensure that the PHY is in a known state prior to
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* startting hardware leveling. Also acts as to latch some state from
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* the EMIF into the PHY.
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*/
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writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
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writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
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writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
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clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
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EMIF_REG_INITREF_DIS_MASK);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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/* Perform hardware leveling. */
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udelay(1000);
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writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
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0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
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writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
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0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
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writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
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/* Enable read leveling */
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writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
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/*
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* Enable full read and write leveling. Wait for read and write
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* leveling bit to clear RDWRLVLFULL_START bit 31
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*/
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while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
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;
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/* Check the timeout register to see if leveling is complete */
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if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
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puts("DDR3 H/W leveling incomplete with errors\n");
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
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configure_mr(nr, 0);
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@ -123,21 +158,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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void config_sdram(const struct emif_regs *regs, int nr)
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{
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if (regs->zq_config) {
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/*
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* A value of 0x2800 for the REF CTRL will give us
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* about 570us for a delay, which will be long enough
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* to configure things.
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*/
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writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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}
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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}
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/**
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@ -153,46 +182,55 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
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writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
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}
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void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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{
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}
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/*
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* Configure EXT PHY registers
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* Configure EXT PHY registers for hardware leveling
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*/
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static void ext_phy_settings(const struct emif_regs *regs, int nr)
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{
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u32 *ext_phy_ctrl_base = 0;
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u32 *emif_ext_phy_ctrl_base = 0;
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const u32 *ext_phy_ctrl_const_regs;
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u32 i = 0;
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u32 size;
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ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
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emif_ext_phy_ctrl_base =
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(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
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/* Configure external phy control timing registers */
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for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
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writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
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/* Update shadow registers */
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writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
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}
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/*
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* Enable hardware leveling on the EMIF. For details about these
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* magic values please see the EMIF registers section of the TRM.
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*/
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writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
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writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
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writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
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writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
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writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
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writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
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writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
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writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
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writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
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writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
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writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
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writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
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/*
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* external phy 6-24 registers do not change with
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* ddr frequency
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* Sequence to ensure that the PHY is again in a known state after
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* hardware leveling.
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*/
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emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
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if (!size)
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return;
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for (i = 0; i < size; i++) {
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writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
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/* Update shadow registers */
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writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
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}
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writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
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writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
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writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
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}
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/**
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@ -201,11 +239,17 @@ static void ext_phy_settings(const struct emif_regs *regs, int nr)
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void config_ddr_phy(const struct emif_regs *regs, int nr)
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{
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/*
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* disable initialization and refreshes for now until we
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* Disable initialization and refreshes for now until we
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* finish programming EMIF regs.
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* Also set time between rising edge of DDR_RESET to rising
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* edge of DDR_CKE to > 500us per memory spec.
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*/
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#ifndef CONFIG_AM43XX
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setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
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EMIF_REG_INITREF_DIS_MASK);
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#endif
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if (regs->zq_config)
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writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->emif_ddr_phy_ctlr_1,
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&emif_reg[nr]->emif_ddr_phy_ctrl_1);
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@ -112,17 +112,20 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
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/* Set CKE to be controlled by EMIF/DDR PHY */
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writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
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#endif
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#ifdef CONFIG_AM43XX
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writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
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while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
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;
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writel(0x80000000, &ddrctrl->ddrioctrl);
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config_io_ctrl(ioregs);
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/* Set CKE to be controlled by EMIF/DDR PHY */
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writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
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/* Allow EMIF to control DDR_RESET */
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writel(0x00000000, &ddrctrl->ddrioctrl);
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#endif
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/* Program EMIF instance */
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@ -219,6 +219,12 @@ struct cm_dpll {
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unsigned int resv4[2];
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unsigned int clklcdcpixelclk; /* offset 0x34 */
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};
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struct prm_device_inst {
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unsigned int prm_rstctrl;
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unsigned int prm_rsttime;
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unsigned int prm_rstst;
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};
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#else
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/* Encapsulating core pll registers */
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struct cm_wkuppll {
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@ -386,6 +392,11 @@ struct cm_device_inst {
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unsigned int cm_dll_ctrl;
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};
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struct prm_device_inst {
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unsigned int prm_rstctrl;
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unsigned int prm_rstst;
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};
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struct cm_dpll {
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unsigned int resv1;
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unsigned int clktimer2clk; /* offset 0x04 */
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@ -39,6 +39,7 @@
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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#define PRM_DEVICE_INST 0x44E00F00
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x44E12000
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@ -71,6 +71,7 @@
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#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
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#define USBPHYOCPSCP_MODULE_EN (1 << 1)
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#define CM_DEVICE_INST 0x44df4100
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#define PRM_DEVICE_INST 0x44df4000
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/* Control status register */
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#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
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@ -650,8 +650,8 @@ struct emif_reg_struct {
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u32 emif_rd_wr_exec_thresh;
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u32 emif_cos_config;
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u32 padding9[6];
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u32 emif_ddr_phy_status[21];
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u32 padding10[27];
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u32 emif_ddr_phy_status[28];
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u32 padding10[20];
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u32 emif_ddr_ext_phy_ctrl_1;
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u32 emif_ddr_ext_phy_ctrl_1_shdw;
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u32 emif_ddr_ext_phy_ctrl_2;
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@ -700,9 +700,36 @@ struct emif_reg_struct {
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u32 emif_ddr_ext_phy_ctrl_23_shdw;
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u32 emif_ddr_ext_phy_ctrl_24;
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u32 emif_ddr_ext_phy_ctrl_24_shdw;
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u32 padding[22];
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u32 emif_ddr_fifo_misaligned_clear_1;
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u32 emif_ddr_fifo_misaligned_clear_2;
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u32 emif_ddr_ext_phy_ctrl_25;
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u32 emif_ddr_ext_phy_ctrl_25_shdw;
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u32 emif_ddr_ext_phy_ctrl_26;
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u32 emif_ddr_ext_phy_ctrl_26_shdw;
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u32 emif_ddr_ext_phy_ctrl_27;
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u32 emif_ddr_ext_phy_ctrl_27_shdw;
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u32 emif_ddr_ext_phy_ctrl_28;
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u32 emif_ddr_ext_phy_ctrl_28_shdw;
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u32 emif_ddr_ext_phy_ctrl_29;
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u32 emif_ddr_ext_phy_ctrl_29_shdw;
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u32 emif_ddr_ext_phy_ctrl_30;
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u32 emif_ddr_ext_phy_ctrl_30_shdw;
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u32 emif_ddr_ext_phy_ctrl_31;
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u32 emif_ddr_ext_phy_ctrl_31_shdw;
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u32 emif_ddr_ext_phy_ctrl_32;
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u32 emif_ddr_ext_phy_ctrl_32_shdw;
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u32 emif_ddr_ext_phy_ctrl_33;
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u32 emif_ddr_ext_phy_ctrl_33_shdw;
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u32 emif_ddr_ext_phy_ctrl_34;
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u32 emif_ddr_ext_phy_ctrl_34_shdw;
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u32 emif_ddr_ext_phy_ctrl_35;
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u32 emif_ddr_ext_phy_ctrl_35_shdw;
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union {
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u32 emif_ddr_ext_phy_ctrl_36;
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u32 emif_ddr_fifo_misaligned_clear_1;
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};
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union {
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u32 emif_ddr_ext_phy_ctrl_36_shdw;
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u32 emif_ddr_fifo_misaligned_clear_2;
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};
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};
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struct dmm_lisa_map_regs {
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@ -21,6 +21,7 @@
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#include "board.h"
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#include <power/pmic.h>
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#include <power/tps65218.h>
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#include <power/tps62362.h>
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#include <miiphy.h>
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#include <cpsw.h>
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@ -81,12 +82,12 @@ static int read_eeprom(struct am43xx_board_id *header)
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const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
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{ /* 19.2 MHz */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
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{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
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{-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
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{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
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{150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
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{125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
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{625, 11, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 24 MHz */
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{300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
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@ -115,24 +116,32 @@ const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
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};
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const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
|
||||
{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
|
||||
{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
|
||||
{1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
|
||||
{1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
|
||||
};
|
||||
|
||||
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
|
||||
{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
|
||||
{960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
|
||||
{960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
|
||||
{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
|
||||
{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
|
||||
{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
|
||||
{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
|
||||
};
|
||||
|
||||
const struct dpll_params epos_evm_dpll_ddr = {
|
||||
266, 24, 1, -1, 1, -1, -1};
|
||||
const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
|
||||
{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
|
||||
{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
|
||||
{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
|
||||
{133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
|
||||
};
|
||||
|
||||
const struct dpll_params gp_evm_dpll_ddr = {
|
||||
400, 23, 1, -1, 1, -1, -1};
|
||||
50, 2, 1, -1, 2, -1, -1};
|
||||
|
||||
static const struct dpll_params idk_dpll_ddr = {
|
||||
400, 23, 1, -1, 2, -1, -1
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs_lpddr2 = {
|
||||
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
|
||||
|
|
@ -157,7 +166,7 @@ const struct emif_regs emif_regs_lpddr2 = {
|
|||
.emif_rd_wr_lvl_rmp_win = 0x0,
|
||||
.emif_rd_wr_lvl_rmp_ctl = 0x0,
|
||||
.emif_rd_wr_lvl_ctl = 0x0,
|
||||
.emif_ddr_phy_ctlr_1 = 0x0E084006,
|
||||
.emif_ddr_phy_ctlr_1 = 0x0E284006,
|
||||
.emif_rd_wr_exec_thresh = 0x80000405,
|
||||
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
|
||||
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
|
||||
|
|
@ -170,29 +179,6 @@ const struct emif_regs emif_regs_lpddr2 = {
|
|||
.emif_cos_config = 0x000FFFFF
|
||||
};
|
||||
|
||||
const u32 ext_phy_ctrl_const_base_lpddr2[] = {
|
||||
0x00500050,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x40001000,
|
||||
0x08102040
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs_ddr3 = {
|
||||
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
|
||||
.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
|
||||
|
|
@ -201,7 +187,7 @@ const struct ctrl_ioregs ioregs_ddr3 = {
|
|||
.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
|
||||
.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
|
||||
.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
|
||||
.emif_sdram_config_ext = 0x0143,
|
||||
.emif_sdram_config_ext = 0xc163,
|
||||
};
|
||||
|
||||
const struct emif_regs ddr3_emif_regs_400Mhz = {
|
||||
|
|
@ -301,150 +287,32 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
|
|||
.emif_cos_config = 0x000FFFFF
|
||||
};
|
||||
|
||||
const u32 ext_phy_ctrl_const_base_ddr3[] = {
|
||||
0x00400040,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00340034,
|
||||
0x00340034,
|
||||
0x00340034,
|
||||
0x00340034,
|
||||
0x00340034,
|
||||
0x0,
|
||||
0x0,
|
||||
0x40000000,
|
||||
0x08102040
|
||||
static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
|
||||
.sdram_config = 0x61a11b32,
|
||||
.sdram_config2 = 0x00000000,
|
||||
.ref_ctrl = 0x00000c30,
|
||||
.sdram_tim1 = 0xeaaad4db,
|
||||
.sdram_tim2 = 0x266b7fda,
|
||||
.sdram_tim3 = 0x107f8678,
|
||||
.read_idle_ctrl = 0x00050000,
|
||||
.zq_config = 0x50074be4,
|
||||
.temp_alert_config = 0x00000000,
|
||||
.emif_ddr_phy_ctlr_1 = 0x00008009,
|
||||
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
|
||||
.emif_ddr_ext_phy_ctrl_2 = 0x00000040,
|
||||
.emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
|
||||
.emif_ddr_ext_phy_ctrl_4 = 0x00000051,
|
||||
.emif_ddr_ext_phy_ctrl_5 = 0x00000051,
|
||||
.emif_rd_wr_lvl_rmp_win = 0x00000000,
|
||||
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
|
||||
.emif_rd_wr_lvl_ctl = 0x00000000,
|
||||
.emif_rd_wr_exec_thresh = 0x00000405,
|
||||
.emif_prio_class_serv_map = 0x00000000,
|
||||
.emif_connect_id_serv_1_map = 0x00000000,
|
||||
.emif_connect_id_serv_2_map = 0x00000000,
|
||||
.emif_cos_config = 0x00ffffff
|
||||
};
|
||||
|
||||
const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
|
||||
0x00000000,
|
||||
0x00000045,
|
||||
0x00000046,
|
||||
0x00000048,
|
||||
0x00000047,
|
||||
0x00000000,
|
||||
0x0000004C,
|
||||
0x00000070,
|
||||
0x00000085,
|
||||
0x000000A3,
|
||||
0x00000000,
|
||||
0x0000000C,
|
||||
0x00000030,
|
||||
0x00000045,
|
||||
0x00000063,
|
||||
0x00000000,
|
||||
0x0,
|
||||
0x0,
|
||||
0x40000000,
|
||||
0x08102040
|
||||
};
|
||||
|
||||
const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
|
||||
0x00000000,
|
||||
0x00000044,
|
||||
0x00000044,
|
||||
0x00000046,
|
||||
0x00000046,
|
||||
0x00000000,
|
||||
0x00000059,
|
||||
0x00000077,
|
||||
0x00000093,
|
||||
0x000000A8,
|
||||
0x00000000,
|
||||
0x00000019,
|
||||
0x00000037,
|
||||
0x00000053,
|
||||
0x00000068,
|
||||
0x00000000,
|
||||
0x0,
|
||||
0x0,
|
||||
0x40000000,
|
||||
0x08102040
|
||||
};
|
||||
|
||||
static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
|
||||
/* first 5 are taken care by emif_regs */
|
||||
0x00700070,
|
||||
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
|
||||
0x00800080,
|
||||
0x00800080,
|
||||
|
||||
0x40000000,
|
||||
|
||||
0x08102040,
|
||||
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
|
||||
{
|
||||
if (board_is_eposevm()) {
|
||||
*regs = ext_phy_ctrl_const_base_lpddr2;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
|
||||
} else if (board_is_evm_14_or_later()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3_production;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
|
||||
} else if (board_is_evm_12_or_later()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3_beta;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
|
||||
} else if (board_is_gpevm()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
|
||||
} else if (board_is_sk()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3_sk;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
if (board_is_eposevm())
|
||||
return &epos_evm_dpll_ddr;
|
||||
else if (board_is_gpevm() || board_is_sk())
|
||||
return &gp_evm_dpll_ddr;
|
||||
|
||||
printf(" Board '%s' not supported\n", am43xx_board_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_sys_clk_index : returns the index of the sys_clk read from
|
||||
* ctrl status register. This value is either
|
||||
|
|
@ -464,6 +332,22 @@ static u32 get_sys_clk_index(void)
|
|||
CTRL_SYSBOOT_15_14_SHIFT);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
int ind = get_sys_clk_index();
|
||||
|
||||
if (board_is_eposevm())
|
||||
return &epos_evm_dpll_ddr[ind];
|
||||
else if (board_is_gpevm() || board_is_sk())
|
||||
return &gp_evm_dpll_ddr;
|
||||
else if (board_is_idk())
|
||||
return &idk_dpll_ddr;
|
||||
|
||||
printf(" Board '%s' not supported\n", am43xx_board_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* get_opp_offset:
|
||||
* Returns the index for safest OPP of the device to boot.
|
||||
|
|
@ -513,10 +397,86 @@ const struct dpll_params *get_dpll_per_params(void)
|
|||
return &dpll_per[ind];
|
||||
}
|
||||
|
||||
void scale_vcores_generic(u32 m)
|
||||
{
|
||||
int mpu_vdd;
|
||||
|
||||
if (i2c_probe(TPS65218_CHIP_PM))
|
||||
return;
|
||||
|
||||
switch (m) {
|
||||
case 1000:
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
|
||||
break;
|
||||
case 800:
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
|
||||
break;
|
||||
case 720:
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
|
||||
break;
|
||||
case 600:
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
|
||||
break;
|
||||
case 300:
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
|
||||
break;
|
||||
default:
|
||||
puts("Unknown MPU clock, not scaling\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set DCDC1 (CORE) voltage to 1.1V */
|
||||
if (tps65218_voltage_update(TPS65218_DCDC1,
|
||||
TPS65218_DCDC_VOLT_SEL_1100MV)) {
|
||||
printf("%s failure\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set DCDC2 (MPU) voltage */
|
||||
if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
|
||||
printf("%s failure\n", __func__);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void scale_vcores_idk(u32 m)
|
||||
{
|
||||
int mpu_vdd;
|
||||
|
||||
if (i2c_probe(TPS62362_I2C_ADDR))
|
||||
return;
|
||||
|
||||
switch (m) {
|
||||
case 1000:
|
||||
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
|
||||
break;
|
||||
case 800:
|
||||
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
|
||||
break;
|
||||
case 720:
|
||||
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
|
||||
break;
|
||||
case 600:
|
||||
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
|
||||
break;
|
||||
case 300:
|
||||
mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
|
||||
break;
|
||||
default:
|
||||
puts("Unknown MPU clock, not scaling\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set VDD_MPU voltage */
|
||||
if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
|
||||
printf("%s failure\n", __func__);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void scale_vcores(void)
|
||||
{
|
||||
const struct dpll_params *mpu_params;
|
||||
int mpu_vdd;
|
||||
struct am43xx_board_id header;
|
||||
|
||||
enable_i2c0_pin_mux();
|
||||
|
|
@ -527,30 +487,10 @@ void scale_vcores(void)
|
|||
/* Get the frequency */
|
||||
mpu_params = get_dpll_mpu_params();
|
||||
|
||||
if (i2c_probe(TPS65218_CHIP_PM))
|
||||
return;
|
||||
|
||||
if (mpu_params->m == 1000) {
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
|
||||
} else if (mpu_params->m == 600) {
|
||||
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
|
||||
} else {
|
||||
puts("Unknown MPU clock, not scaling\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set DCDC1 (CORE) voltage to 1.1V */
|
||||
if (tps65218_voltage_update(TPS65218_DCDC1,
|
||||
TPS65218_DCDC_VOLT_SEL_1100MV)) {
|
||||
puts("tps65218_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set DCDC2 (MPU) voltage */
|
||||
if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
|
||||
puts("tps65218_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
if (board_is_idk())
|
||||
scale_vcores_idk(mpu_params->m);
|
||||
else
|
||||
scale_vcores_generic(mpu_params->m);
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
|
|
@ -602,6 +542,9 @@ void sdram_init(void)
|
|||
} else if (board_is_sk()) {
|
||||
config_ddr(400, &ioregs_ddr3, NULL, NULL,
|
||||
&ddr3_sk_emif_regs_400Mhz, 0);
|
||||
} else if (board_is_idk()) {
|
||||
config_ddr(400, &ioregs_ddr3, NULL, NULL,
|
||||
&ddr3_idk_emif_regs_400Mhz, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -611,10 +554,17 @@ int power_init_board(void)
|
|||
{
|
||||
struct pmic *p;
|
||||
|
||||
power_tps65218_init(I2C_PMIC);
|
||||
p = pmic_get("TPS65218_PMIC");
|
||||
if (p && !pmic_probe(p))
|
||||
puts("PMIC: TPS65218\n");
|
||||
if (board_is_idk()) {
|
||||
power_tps62362_init(I2C_PMIC);
|
||||
p = pmic_get("TPS62362");
|
||||
if (p && !pmic_probe(p))
|
||||
puts("PMIC: TPS62362\n");
|
||||
} else {
|
||||
power_tps65218_init(I2C_PMIC);
|
||||
p = pmic_get("TPS65218_PMIC");
|
||||
if (p && !pmic_probe(p))
|
||||
puts("PMIC: TPS65218\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -771,6 +721,10 @@ int board_eth_init(bd_t *bis)
|
|||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
cpsw_slaves[0].phy_addr = 4;
|
||||
cpsw_slaves[1].phy_addr = 5;
|
||||
} else if (board_is_idk()) {
|
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
cpsw_slaves[0].phy_addr = 0;
|
||||
} else {
|
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,11 @@ static inline int board_is_sk(void)
|
|||
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_idk(void)
|
||||
{
|
||||
return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_evm_14_or_later(void)
|
||||
{
|
||||
return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ void enable_board_pin_mux(void)
|
|||
#if defined(CONFIG_NAND)
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#endif
|
||||
} else if (board_is_sk()) {
|
||||
} else if (board_is_sk() || board_is_idk()) {
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
#if defined(CONFIG_NAND)
|
||||
printf("Error: NAND flash not present on this board\n");
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <ns16550.h>
|
||||
#include <twl4030.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
|
|
@ -43,6 +45,17 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
|
|||
0
|
||||
};
|
||||
|
||||
static const struct ns16550_platdata devkit8000_serial = {
|
||||
OMAP34XX_UART3,
|
||||
2,
|
||||
V_NS16550_CLK
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(devkit8000_uart) = {
|
||||
"serial_omap",
|
||||
&devkit8000_serial
|
||||
};
|
||||
|
||||
/*
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
|
|
|
|||
|
|
@ -304,6 +304,11 @@ Platform specific options
|
|||
Thus BCH16 can be supported on 4K page NAND.
|
||||
|
||||
|
||||
CONFIG_NAND_OMAP_GPMC_PREFETCH
|
||||
On OMAP platforms that use the GPMC controller
|
||||
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
|
||||
uses the prefetch mode to speed up read operations.
|
||||
|
||||
NOTE:
|
||||
=====
|
||||
|
||||
|
|
|
|||
|
|
@ -441,6 +441,115 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
|
|||
return (err) ? err : error_count;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
|
||||
|
||||
#define PREFETCH_CONFIG1_CS_SHIFT 24
|
||||
#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
|
||||
#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
|
||||
#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
|
||||
#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
|
||||
#define ENABLE_PREFETCH (1 << 7)
|
||||
|
||||
/**
|
||||
* omap_prefetch_enable - configures and starts prefetch transfer
|
||||
* @fifo_th: fifo threshold to be used for read/ write
|
||||
* @count: number of bytes to be transferred
|
||||
* @is_write: prefetch read(0) or write post(1) mode
|
||||
* @cs: chip select to use
|
||||
*/
|
||||
static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
if (readl(&gpmc_cfg->prefetch_control))
|
||||
return -EBUSY;
|
||||
|
||||
/* Set the amount of bytes to be prefetched */
|
||||
writel(count, &gpmc_cfg->prefetch_config2);
|
||||
|
||||
val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
|
||||
PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
|
||||
writel(val, &gpmc_cfg->prefetch_config1);
|
||||
|
||||
/* Start the prefetch engine */
|
||||
writel(1, &gpmc_cfg->prefetch_control);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_prefetch_reset - disables and stops the prefetch engine
|
||||
*/
|
||||
static void omap_prefetch_reset(void)
|
||||
{
|
||||
writel(0, &gpmc_cfg->prefetch_control);
|
||||
writel(0, &gpmc_cfg->prefetch_config1);
|
||||
}
|
||||
|
||||
static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
|
||||
{
|
||||
int ret;
|
||||
uint32_t cnt;
|
||||
struct omap_nand_info *info = chip->priv;
|
||||
|
||||
ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
do {
|
||||
int i;
|
||||
|
||||
cnt = readl(&gpmc_cfg->prefetch_status);
|
||||
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
|
||||
|
||||
for (i = 0; i < cnt / 4; i++) {
|
||||
*buf++ = readl(CONFIG_SYS_NAND_BASE);
|
||||
len -= 4;
|
||||
}
|
||||
} while (len);
|
||||
|
||||
omap_prefetch_reset();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
|
||||
{
|
||||
int ret;
|
||||
uint32_t head, tail;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
/*
|
||||
* If the destination buffer is unaligned, start with reading
|
||||
* the overlap byte-wise.
|
||||
*/
|
||||
head = ((uint32_t) buf) % 4;
|
||||
if (head) {
|
||||
nand_read_buf(mtd, buf, head);
|
||||
buf += head;
|
||||
len -= head;
|
||||
}
|
||||
|
||||
/*
|
||||
* Only transfer multiples of 4 bytes in a pre-fetched fashion.
|
||||
* If there's a residue, care for it byte-wise afterwards.
|
||||
*/
|
||||
tail = len % 4;
|
||||
|
||||
ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
|
||||
if (ret < 0) {
|
||||
/* fallback in case the prefetch engine is busy */
|
||||
nand_read_buf(mtd, buf, len);
|
||||
} else if (tail) {
|
||||
buf += len - tail;
|
||||
nand_read_buf(mtd, buf, tail);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
|
||||
|
||||
/**
|
||||
* omap_read_page_bch - hardware ecc based page read function
|
||||
* @mtd: mtd info structure
|
||||
|
|
@ -880,11 +989,12 @@ int board_nand_init(struct nand_chip *nand)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
|
||||
/* TODO: Implement for 16-bit bus width */
|
||||
if (nand->options & NAND_BUSWIDTH_16)
|
||||
nand->read_buf = nand_read_buf16;
|
||||
else
|
||||
nand->read_buf = nand_read_buf;
|
||||
nand->read_buf = omap_nand_read_prefetch8;
|
||||
#endif
|
||||
|
||||
nand->dev_ready = omap_dev_ready;
|
||||
|
|
|
|||
|
|
@ -14,5 +14,6 @@ obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
|
|||
obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
|
||||
obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
|
||||
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
|
||||
obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
|
||||
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
|
||||
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
|
||||
* Author: Felipe Balbi <balbi@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/errno.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/tps62362.h>
|
||||
|
||||
/**
|
||||
* tps62362_voltage_update() - Function to change a voltage level, as this
|
||||
* is a multi-step process.
|
||||
* @reg: Register address to write to
|
||||
* @volt_sel: Voltage register value to write
|
||||
* @return: 0 on success, 1 on failure
|
||||
*/
|
||||
int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel)
|
||||
{
|
||||
if (reg > TPS62362_NUM_REGS)
|
||||
return 1;
|
||||
|
||||
return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1);
|
||||
}
|
||||
|
||||
int power_tps62362_init(unsigned char bus)
|
||||
{
|
||||
static const char name[] = "TPS62362";
|
||||
struct pmic *p = pmic_alloc();
|
||||
|
||||
if (!p) {
|
||||
printf("%s: POWER allocation error!\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
p->name = name;
|
||||
p->interface = PMIC_I2C;
|
||||
p->number_of_regs = TPS62362_NUM_REGS;
|
||||
p->hw.i2c.addr = TPS62362_I2C_ADDR;
|
||||
p->hw.i2c.tx_num = 1;
|
||||
p->bus = bus;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -39,6 +39,7 @@
|
|||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_TPS65218
|
||||
#define CONFIG_POWER_TPS62362
|
||||
|
||||
/* SPL defines. */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40300350
|
||||
|
|
@ -235,6 +236,8 @@
|
|||
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
|
||||
"if test $board_name = AM43__SK; then " \
|
||||
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
|
||||
"if test $board_name = AM43_IDK; then " \
|
||||
"setenv fdtfile am437x-idk-evm.dtb; fi; " \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine device tree; fi; \0"
|
||||
|
||||
|
|
|
|||
|
|
@ -16,12 +16,8 @@
|
|||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */
|
||||
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
|
||||
#define CONFIG_OMAP_GPIO
|
||||
#define CONFIG_OMAP_COMMON
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
/*
|
||||
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||
|
|
@ -31,31 +27,31 @@
|
|||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80100000
|
||||
|
||||
#define CONFIG_SDRC /* The chip has SDRC controller */
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap3.h>
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
|
||||
|
||||
#define CONFIG_NAND
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
|
||||
|
||||
#include <configs/ti_omap3_common.h>
|
||||
|
||||
/* Display CPU and Board information */
|
||||
#define CONFIG_DISPLAY_CPUINFO 1
|
||||
#define CONFIG_DISPLAY_BOARDINFO 1
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_REVISION_TAG 1
|
||||
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
/* Sector */
|
||||
#undef CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
|
||||
|
||||
/* Hardware drivers */
|
||||
|
|
@ -69,39 +65,18 @@
|
|||
#define CONFIG_DM9000_NO_SROM 1
|
||||
#undef CONFIG_DM9000_DEBUG
|
||||
|
||||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3 3
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_GENERIC_MMC 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_OMAP_HSMMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
/* SPI */
|
||||
#undef CONFIG_SPI
|
||||
#undef CONFIG_OMAP3_SPI
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||
#undef CONFIG_SYS_I2C_OMAP24XX
|
||||
#define CONFIG_SYS_I2C_OMAP34XX
|
||||
|
||||
/* TWL4030 */
|
||||
#define CONFIG_TWL4030_POWER 1
|
||||
#define CONFIG_TWL4030_LED 1
|
||||
|
||||
/* Board NAND Info */
|
||||
#define CONFIG_SYS_NO_FLASH /* no NOR flash */
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define MTDIDS_DEFAULT "nand0=nand"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:" \
|
||||
"512k(x-loader)," \
|
||||
|
|
@ -110,14 +85,8 @@
|
|||
"4m(kernel)," \
|
||||
"-(fs)"
|
||||
|
||||
#define CONFIG_NAND_OMAP_GPMC
|
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
|
||||
/* to access nand */
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access nand at */
|
||||
/* CS0 */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
|
||||
/* devices */
|
||||
#define CONFIG_JFFS2_NAND
|
||||
/* nand device jffs2 lives on */
|
||||
#define CONFIG_JFFS2_DEV "nand0"
|
||||
|
|
@ -127,20 +96,20 @@
|
|||
/* partition */
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP /* DHCP support */
|
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */
|
||||
#define CONFIG_CMD_FAT /* FAT support */
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */
|
||||
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
|
||||
#define CONFIG_CMD_MMC /* MMC support */
|
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
|
||||
#define CONFIG_CMD_NAND /* NAND support */
|
||||
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
|
||||
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_IMI /* iminfo */
|
||||
#undef CONFIG_CMD_SPI
|
||||
#undef CONFIG_CMD_GPIO
|
||||
#undef CONFIG_CMD_ASKENV
|
||||
#undef CONFIG_CMD_BOOTZ
|
||||
#undef CONFIG_SUPPORT_RAW_INITRD
|
||||
#undef CONFIG_FAT_WRITE
|
||||
#undef CONFIG_CMD_EXT4
|
||||
#undef CONFIG_CMD_FS_GENERIC
|
||||
|
||||
/* BOOTP/DHCP options */
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
|
|
@ -157,10 +126,6 @@
|
|||
#undef CONFIG_BOOTP_VENDOREX
|
||||
|
||||
/* Environment information */
|
||||
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
|
|
@ -228,88 +193,29 @@
|
|||
|
||||
#define CONFIG_BOOTCOMMAND "run autoboot"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
0x01000000) /* 16MB */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
|
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
||||
|
||||
/* NAND and environment organization */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
|
||||
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* SRAM config */
|
||||
#define CONFIG_SYS_SRAM_START 0x40200000
|
||||
#define CONFIG_SYS_SRAM_SIZE 0x10000
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_ECC
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
||||
#undef CONFIG_SPL_MTD_SUPPORT
|
||||
|
||||
#undef CONFIG_SPL_TEXT_BASE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
|
||||
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
|
||||
#undef CONFIG_SPL_STACK
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
|
@ -325,30 +231,23 @@
|
|||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
|
||||
|
||||
/* SPL OS boot options */
|
||||
#define CONFIG_SPL_OS_BOOT
|
||||
|
||||
#define CONFIG_CMD_SPL
|
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
|
||||
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
|
||||
0x400000)
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
|
||||
|
||||
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
|
||||
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
|
||||
|
||||
#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
|
||||
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
|
||||
#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
|
||||
|
||||
#undef CONFIG_SYS_SPL_ARGS_ADDR
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -45,6 +45,9 @@
|
|||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
|
|
@ -65,17 +68,21 @@
|
|||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript;" \
|
||||
"else " \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"fi ;" \
|
||||
"fi;" \
|
||||
|
||||
/* Clock Defines */
|
||||
|
|
|
|||
|
|
@ -85,10 +85,16 @@
|
|||
"vram=${vram} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
|
|
@ -110,6 +116,13 @@
|
|||
"bootz ${loadaddr} - ${fdtaddr}; " \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"set env autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"tftp ${fdtaddr} ${fdtfile}; " \
|
||||
"run netargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"findfdt="\
|
||||
"if test $board_name = omap5_uevm; then " \
|
||||
"setenv fdtfile omap5-uevm.dtb; fi; " \
|
||||
|
|
|
|||
|
|
@ -66,7 +66,11 @@ struct gpmc {
|
|||
u32 status; /* 0x54 */
|
||||
u8 res5[0x8]; /* 0x58 */
|
||||
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
|
||||
u8 res6[0x14]; /* 0x1E0 */
|
||||
u32 prefetch_config1; /* 0x1E0 */
|
||||
u32 prefetch_config2; /* 0x1E4 */
|
||||
u32 res6; /* 0x1E8 */
|
||||
u32 prefetch_control; /* 0x1EC */
|
||||
u32 prefetch_status; /* 0x1F0 */
|
||||
u32 ecc_config; /* 0x1F4 */
|
||||
u32 ecc_control; /* 0x1F8 */
|
||||
u32 ecc_size_config; /* 0x1FC */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
|
||||
* Author: Felipe Balbi <balbi@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __POWER_TPS62362_H__
|
||||
#define __POWER_TPS62362_H__
|
||||
|
||||
/* I2C chip address */
|
||||
#define TPS62362_I2C_ADDR 0x60
|
||||
|
||||
/* Registers */
|
||||
#define TPS62362_SET0 0x00
|
||||
#define TPS62362_SET1 0x01
|
||||
#define TPS62362_SET2 0x02
|
||||
#define TPS62362_SET3 0x03
|
||||
#define TPS62362_NUM_REGS 4
|
||||
|
||||
#define TPS62362_DCDC_VOLT_SEL_0950MV 0x12
|
||||
#define TPS62362_DCDC_VOLT_SEL_1100MV 0x21
|
||||
#define TPS62362_DCDC_VOLT_SEL_1200MV 0x2b
|
||||
#define TPS62362_DCDC_VOLT_SEL_1260MV 0x31
|
||||
#define TPS62362_DCDC_VOLT_SEL_1330MV 0x38
|
||||
|
||||
int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel);
|
||||
int power_tps62362_init(unsigned char bus);
|
||||
#endif /* __POWER_TPS62362_H__ */
|
||||
|
|
@ -54,7 +54,10 @@ enum {
|
|||
|
||||
#define TPS65218_MASK_ALL_BITS 0xFF
|
||||
|
||||
#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a
|
||||
#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
|
||||
#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23
|
||||
#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29
|
||||
#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
|
||||
|
||||
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
|
||||
|
|
|
|||
Loading…
Reference in New Issue