SPI: mxc_spi: replace fixed offsets with structures
This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de>
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@ -64,6 +64,17 @@ struct gpio_regs {
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u32 gpio_psr;
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};
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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#define IOMUX_PADNUM_MASK 0x1ff
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#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
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@ -265,6 +265,18 @@ struct gpt_regs {
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u32 counter; /* counter */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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/* Watchdog Timer (WDOG) registers */
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struct wdog_regs {
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u16 wcr; /* Control */
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@ -256,6 +256,18 @@ struct src {
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u32 simr;
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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struct iim_regs {
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u32 stat;
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u32 statm;
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@ -36,16 +36,6 @@
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#include <asm/arch/mx31.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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@ -76,15 +66,6 @@ static unsigned long spi_bases[] = {
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPICON 0x0C
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#define MXC_CSPIINT 0x10
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#define MXC_CSPIDMA 0x14
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#define MXC_CSPISTAT 0x18
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#define MXC_CSPIPERIOD 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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@ -119,16 +100,6 @@ static unsigned long spi_bases[] = {
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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@ -158,6 +129,9 @@ static unsigned long spi_bases[] = {
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#define OUT MXC_GPIO_DIRECTION_OUT
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#define reg_read readl
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#define reg_write(a, v) writel(v, a)
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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@ -174,16 +148,6 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
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return container_of(slave, struct mxc_spi_slave, slave);
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}
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static inline u32 reg_read(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline void reg_write(unsigned long addr, u32 val)
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{
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*(volatile unsigned long*)addr = val;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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@ -254,17 +218,18 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
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u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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if (max_hz == 0) {
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printf("Error: desired clock is 0\n");
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return -1;
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}
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reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
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reg_ctrl = reg_read(®s->ctrl);
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/* Reset spi */
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reg_write(mxcs->base + MXC_CSPICTRL, 0);
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reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
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reg_write(®s->ctrl, 0);
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reg_write(®s->ctrl, (reg_ctrl | 0x1));
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/*
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* The following computation is taken directly from Freescale's code.
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@ -312,7 +277,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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if (mode & SPI_CPHA)
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sclkpha = 1;
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reg_config = reg_read(mxcs->base + MXC_CSPICON);
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reg_config = reg_read(®s->cfg);
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/*
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* Configuration register setup
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@ -326,18 +291,17 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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(sclkpha << (cs + MXC_CSPICON_PHA));
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debug("reg_ctrl = 0x%x\n", reg_ctrl);
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reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
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reg_write(®s->ctrl, reg_ctrl);
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debug("reg_config = 0x%x\n", reg_config);
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reg_write(mxcs->base + MXC_CSPICON, reg_config);
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reg_write(®s->cfg, reg_config);
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/* save config register and control register */
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mxcs->ctrl_reg = reg_ctrl;
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mxcs->cfg_reg = reg_config;
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/* clear interrupt reg */
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reg_write(mxcs->base + MXC_CSPIINT, 0);
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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reg_write(®s->intr, 0);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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return 0;
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}
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@ -349,6 +313,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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int nbytes = (bitlen + 7) / 8;
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u32 data, cnt, i;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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debug("%s: bitlen %d dout 0x%x din 0x%x\n",
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__func__, bitlen, (u32)dout, (u32)din);
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@ -357,14 +322,13 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef CONFIG_MX51
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reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
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reg_write(®s->cfg, mxcs->cfg_reg);
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#endif
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/* Clear interrupt register */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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/*
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* The SPI controller works only with words,
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@ -381,7 +345,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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reg_write(®s->txdata, data);
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nbytes -= cnt;
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}
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@ -402,28 +366,27 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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dout += 4;
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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reg_write(®s->txdata, data);
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nbytes -= 4;
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}
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/* FIFO is written, now starts the transfer setting the XCH bit */
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
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reg_write(®s->ctrl, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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/* Wait until the TC (Transfer completed) bit is set */
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while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
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while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
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;
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/* Transfer completed, clear any pending request */
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reg_write(mxcs->base + MXC_CSPISTAT,
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MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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nbytes = (bitlen + 7) / 8;
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cnt = nbytes % 32;
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if (bitlen % 32) {
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data = reg_read(mxcs->base + MXC_CSPIRXDATA);
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data = reg_read(®s->rxdata);
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cnt = (bitlen % 32) / 8;
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data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
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debug("SPI Rx unaligned: 0x%x\n", data);
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@ -436,7 +399,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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while (nbytes > 0) {
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u32 tmp;
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tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
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tmp = reg_read(®s->rxdata);
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data = cpu_to_be32(tmp);
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debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
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cnt = min(nbytes, sizeof(data));
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@ -468,7 +431,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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spi_cs_activate(slave);
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while (n_bytes > 0) {
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if (n_bytes < MAX_SPI_BYTES)
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blk_size = n_bytes;
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else
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@ -572,13 +534,13 @@ void spi_free_slave(struct spi_slave *slave)
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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reg_write(mxcs->base + MXC_CSPIRESET, 1);
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reg_write(®s->rxdata, 1);
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udelay(1);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
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reg_write(mxcs->base + MXC_CSPIPERIOD,
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MXC_CSPIPERIOD_32KHZ);
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reg_write(mxcs->base + MXC_CSPIINT, 0);
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reg_write(®s->ctrl, mxcs->ctrl_reg);
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reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
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reg_write(®s->intr, 0);
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return 0;
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}
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