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[FIX] remove files form repository

utp
Michal Simek 2007-09-16 20:51:57 +02:00
parent 7201cfc4a7
commit b49c90df6e
5 changed files with 0 additions and 1187 deletions
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374
drivers/net/xilinx_emac.c
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@ -1,374 +0,0 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on Xilinx drivers
*
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <asm/io.h>
#include "xilinx_emac.h"
#ifdef XILINX_EMAC
#undef DEBUG
#define ENET_MAX_MTU PKTSIZE
#define ENET_ADDR_LENGTH 6
static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
static xemac emac;
void eth_halt(void)
{
#ifdef DEBUG
puts ("eth_halt\n");
#endif
}
int eth_init(bd_t * bis)
{
u32 helpreg;
#ifdef DEBUG
printf("EMAC Initialization Started\n\r");
#endif
if (emac.isstarted) {
puts("Emac is started\n");
return 0;
}
memset (&emac, 0, sizeof (xemac));
emac.baseaddress = XILINX_EMAC_BASEADDR;
/* Setting up FIFOs */
emac.recvfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_RXREG_OFFSET;
emac.recvfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_RXDATA_OFFSET;
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
emac.sendfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_TXREG_OFFSET;
emac.sendfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_TXDATA_OFFSET;
out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
/* Reset the entire IPIF */
out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
XIIF_V123B_RESET_MASK);
/* Stopping EMAC for setting up MAC */
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
if (!getenv("ethaddr")) {
memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
}
/* Set the device station address high and low registers */
helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
emac.isstarted = 1;
/* Enable the transmitter, and receiver */
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
printf("EMAC Initialization complete\n\r");
return 0;
}
int eth_send(volatile void *ptr, int len)
{
u32 intrstatus;
u32 xmitstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 *wordbuffer = (u32 *) ptr;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
/*
* Check for overruns and underruns for the transmit status and length
* FIFOs and make sure the send packet FIFO is not deadlocked.
* Any of these conditions is bad enough that we do not want to
* continue. The upper layer software should reset the device to resolve
* the error.
*/
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
#endif
return 0;
} else if (in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
#ifdef DEBUG
puts("Transmitting fifo error\n");
#endif
return 0;
}
/*
* Before writing to the data FIFO, make sure the length FIFO is not
* full. The data FIFO might not be full yet even though the length FIFO
* is. This avoids an overrun condition on the length FIFO and keeps the
* FIFOs in sync.
*
* Clear the latched LFIFO_FULL bit so next time around the most
* current status is represented
*/
if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
#ifdef DEBUG
puts ("Fifo is full\n");
#endif
return 0;
}
/* get the count of how many words may be inserted into the FIFO */
fifocount = in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
wordcount = len >> 2;
extrabytecount = len & 0x3;
if (fifocount < wordcount) {
#ifdef DEBUG
puts ("Sending packet is larger then size of FIFO\n");
#endif
return 0;
}
for (fifocount = 0; fifocount < wordcount; fifocount++) {
out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
}
if (extrabytecount > 0) {
u32 lastword = 0;
u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
if (extrabytecount == 1) {
lastword = extrabytesbuffer[0] << 24;
} else if (extrabytecount == 2) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16;
} else if (extrabytecount == 3) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16 |
extrabytesbuffer[2] << 8;
}
out_be32 (emac.sendfifo.databaseaddress, lastword);
}
/* Loop on the MAC's status to wait for any pause to complete */
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
/* Clear the pause status from the transmit status register */
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
}
/*
* Set the MAC's transmit packet length register to tell it to transmit
*/
out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
/*
* Loop on the MAC's status to wait for the transmit to complete.
* The transmit status is in the FIFO when the XMIT_DONE bit is set.
*/
do {
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
}
while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
#endif
return 0;
}
/* Clear the interrupt status register of transmit statuses */
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_ALL_MASK);
/*
* Collision errors are stored in the transmit status register
* instead of the interrupt status register
*/
if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
#ifdef DEBUG
puts ("Transmitting collision error\n");
#endif
return 0;
}
return 1;
}
int eth_rx(void)
{
u32 pktlength;
u32 intrstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 lastword;
u8 *extrabytesbuffer;
if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
& XPF_DEADLOCK_MASK) {
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
#ifdef DEBUG
puts ("Receiving FIFO deadlock\n");
#endif
return 0;
}
/*
* Get the interrupt status to know what happened (whether an error
* occurred and/or whether frames have been received successfully).
* When clearing the intr status register, clear only statuses that
* pertain to receive.
*/
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
/*
* Before reading from the length FIFO, make sure the length FIFO is not
* empty. We could cause an underrun error if we try to read from an
* empty FIFO.
*/
if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
#ifdef DEBUG
/* puts("Receiving FIFO is empty\n"); */
#endif
return 0;
}
/*
* Determine, from the MAC, the length of the next packet available
* in the data FIFO (there should be a non-zero length here)
*/
pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
if (!pktlength) {
return 0;
}
/*
* Write the RECV_DONE bit in the status register to clear it. This bit
* indicates the RPLR is non-empty, and we know it's set at this point.
* We clear it so that subsequent entry into this routine will reflect
* the current status. This is done because the non-empty bit is latched
* in the IPIF, which means it may indicate a non-empty condition even
* though there is something in the FIFO.
*/
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
XEM_EIR_RECV_DONE_MASK);
fifocount = in_be32 (emac.recvfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
if ((fifocount * 4) < pktlength) {
#ifdef DEBUG
puts ("Receiving FIFO is smaller than packet size.\n");
#endif
return 0;
}
wordcount = pktlength >> 2;
extrabytecount = pktlength & 0x3;
for (fifocount = 0; fifocount < wordcount; fifocount++) {
etherrxbuff[fifocount] =
in_be32 (emac.recvfifo.databaseaddress);
}
/*
* if there are extra bytes to handle, read the last word from the FIFO
* and insert the extra bytes into the buffer
*/
if (extrabytecount > 0) {
extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
lastword = in_be32 (emac.recvfifo.databaseaddress);
/*
* one extra byte in the last word, put the byte into the next
* location of the buffer, bytes in a word of the FIFO are
* ordered from most significant byte to least
*/
if (extrabytecount == 1) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
} else if (extrabytecount == 2) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
extrabytesbuffer[1] = (u8) (lastword >> 16);
} else if (extrabytecount == 3) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
extrabytesbuffer[1] = (u8) (lastword >> 16);
extrabytesbuffer[2] = (u8) (lastword >> 8);
}
}
NetReceive((uchar *)etherrxbuff, pktlength);
return 1;
}
#endif

148
drivers/net/xilinx_emac.h
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@ -1,148 +0,0 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Based on Xilinx drivers
*
*/
typedef struct {
u32 regbaseaddress; /* Base address of registers */
u32 databaseaddress; /* Base address of data for FIFOs */
} xpacketfifov100b;
typedef struct {
u32 baseaddress; /* Base address (of IPIF) */
u32 isstarted; /* Device is currently started 0-no, 1-yes */
xpacketfifov100b recvfifo; /* FIFO used to receive frames */
xpacketfifov100b sendfifo; /* FIFO used to send frames */
} xemac;
#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
#define XIIF_V123B_RESET_MASK 0xAUL
#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
/* This constant is used with the Reset Register */
#define XPF_RESET_FIFO_MASK 0x0000000A
#define XPF_COUNT_STATUS_REG_OFFSET 4UL
/* These constants are used with the Occupancy/Vacancy Count Register. This
* register also contains FIFO status */
#define XPF_COUNT_MASK 0x0000FFFF
#define XPF_DEADLOCK_MASK 0x20000000
/* Offset of the MAC registers from the IPIF base address */
#define XEM_REG_OFFSET 0x1100UL
/*
* Register offsets for the Ethernet MAC. Each register is 32 bits.
*/
#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
#define XEM_PFIFO_OFFSET 0x2000UL
/* Tx registers */
#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
/* Rx registers */
#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
/* Tx keyhole */
#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100)
/* Rx keyhole */
#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200)
/*
* EMAC Interrupt Registers (Status and Enable) masks. These registers are
* part of the IPIF IP Interrupt registers
*/
/* A mask for all transmit interrupts, used in polled mode */
#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
XEM_EIR_XMIT_ERROR_MASK | \
XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
XEM_EIR_XMIT_LFIFO_FULL_MASK)
/* Xmit complete */
#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL
/* Recv complete */
#define XEM_EIR_RECV_DONE_MASK 0x00000002UL
/* Xmit error */
#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL
/* Recv error */
#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL
/* Xmit status fifo empty */
#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL
/* Recv length fifo empty */
#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL
/* Xmit length fifo full */
#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL
/* Recv length fifo overrun */
#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL
/* Recv length fifo underrun */
#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL
/* Xmit status fifo overrun */
#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL
/* Transmit status fifo underrun */
#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL
/* Transmit length fifo overrun */
#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL
/* Transmit length fifo underrun */
#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL
/* Transmit pause pkt received */
#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL
/*
* EMAC Control Register (ECR)
*/
/* Full duplex mode */
#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL
/* Reset transmitter */
#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL
/* Enable transmitter */
#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL
/* Reset receiver */
#define XEM_ECR_RECV_RESET_MASK 0x10000000UL
/* Enable receiver */
#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL
/* Enable PHY */
#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL
/* Enable xmit pad insert */
#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL
/* Enable xmit FCS insert */
#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL
/* Enable unicast addr */
#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL
/* Enable broadcast addr */
#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL
/*
* Transmit Status Register (TSR)
*/
/* Transmit excess deferral */
#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL
/* Transmit late collision */
#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL

376
drivers/net/xilinx_emaclite.c
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@ -1,376 +0,0 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <net.h>
#include <config.h>
#include <asm/io.h>
#ifdef XILINX_EMACLITE_BASEADDR
#undef DEBUG
#define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
#define ENET_ADDR_LENGTH 6
/* EmacLite constants */
#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
#define XEL_TSR_OFFSET 0x07FC /* Tx status */
#define XEL_RSR_OFFSET 0x17FC /* Rx status */
#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK 0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
typedef struct {
unsigned int baseaddress; /* Base address for device (IPIF) */
unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
unsigned char deviceid; /* Unique ID of device - for future */
} xemaclite;
static xemaclite emaclite;
static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
#ifdef CFG_ENV_IS_NOWHERE
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
#endif
void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
{
unsigned int i;
u32 alignbuffer;
u32 *to32ptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
from32ptr = (u32 *) srcptr;
/* Word aligned buffer, no correction needed. */
to32ptr = (u32 *) destptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
to8ptr = (u8 *) to32ptr;
alignbuffer = *from32ptr++;
from8ptr = (u8 *) & alignbuffer;
for (i = 0; i < bytecount; i++) {
*to8ptr++ = *from8ptr++;
}
}
void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
{
unsigned i;
u32 alignbuffer;
u32 *to32ptr = (u32 *) destptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
from32ptr = (u32 *) srcptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
alignbuffer = 0;
to8ptr = (u8 *) & alignbuffer;
from8ptr = (u8 *) from32ptr;
for (i = 0; i < bytecount; i++) {
*to8ptr++ = *from8ptr++;
}
*to32ptr++ = alignbuffer;
}
void eth_halt (void)
{
#ifdef DEBUG
puts ("eth_halt\n");
#endif
}
int eth_init (bd_t * bis)
{
#ifdef DEBUG
puts ("EmacLite Initialization Started\n");
#endif
memset (&emaclite, 0, sizeof (xemaclite));
emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
if (!getenv("ethaddr")) {
memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
}
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
/* Copy MAC address */
xemaclite_alignedwrite (bis->bi_enetaddr,
emaclite.baseaddress, ENET_ADDR_LENGTH);
/* Set the length */
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
XEL_TSR_PROG_MAC_ADDR) != 0) ;
#ifdef XILINX_EMACLITE_TX_PING_PONG
/* The same operation with PONG TX */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_TSR_PROG_MAC_ADDR);
while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
#endif
/*
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
#ifdef XILINX_EMACLITE_RX_PING_PONG
out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_RSR_RECV_IE_MASK);
#endif
#ifdef DEBUG
puts ("EmacLite Initialization complete\n");
#endif
return 0;
}
int xemaclite_txbufferavailable (xemaclite * instanceptr)
{
u32 reg;
u32 txpingbusy;
u32 txpongbusy;
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
reg = in_be32 (instanceptr->baseaddress +
instanceptr->nexttxbuffertouse + 0);
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
reg = in_be32 (instanceptr->baseaddress +
(instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
return (!(txpingbusy && txpongbusy));
}
int eth_send (volatile void *ptr, int len) {
unsigned int reg;
unsigned int baseaddress;
unsigned maxtry = 1000;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
udelay (10);
maxtry--;
}
if (!maxtry) {
printf ("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
#ifdef XILINX_EMACLITE_TX_PING_PONG
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
#endif
return 0;
}
/* Determine the expected TX buffer address */
baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
#ifdef XILINX_EMACLITE_TX_PING_PONG
emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
#ifdef DEBUG
printf ("Send packet from 0x%x\n", baseaddress);
#endif
/* Write the frame to the buffer */
xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 1;
}
#ifdef XILINX_EMACLITE_TX_PING_PONG
/* Switch to second buffer */
baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
#ifdef DEBUG
printf ("Send packet from 0x%x\n", baseaddress);
#endif
/* Write the frame to the buffer */
xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 1;
}
#endif
puts ("Error while sending frame\n");
return 0;
}
int eth_rx (void)
{
unsigned int length;
unsigned int reg;
unsigned int baseaddress;
baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
#ifdef DEBUG
printf ("Testing data at address 0x%x\n", baseaddress);
#endif
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
#ifdef XILINX_EMACLITE_RX_PING_PONG
emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
} else {
#ifndef XILINX_EMACLITE_RX_PING_PONG
#ifdef DEBUG
printf ("No data was available - address 0x%x\n", baseaddress);
#endif
return 0;
#else
baseaddress ^= XEL_BUFFER_OFFSET;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
if ((reg & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) {
#ifdef DEBUG
printf ("No data was available - address 0x%x\n",
baseaddress);
#endif
return 0;
}
#endif
}
/* Get the length of the frame that arrived */
switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
0xFFFF0000 ) >> 16) {
case 0x806:
length = 42 + 20; /* FIXME size of ARP */
#ifdef DEBUG
puts ("ARP Packet\n");
#endif
break;
case 0x800:
length = 14 + 14 +
(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
0xFFFF0000) >> 16); /* FIXME size of IP packet */
#ifdef DEBUG
puts("IP Packet\n");
#endif
break;
default:
#ifdef DEBUG
puts("Other Packet\n");
#endif
length = ENET_MAX_MTU;
break;
}
xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
etherrxbuff, length);
/* Acknowledge the frame */
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
reg &= ~XEL_RSR_RECV_DONE_MASK;
out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
#ifdef DEBUG
printf ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
#endif
NetReceive ((uchar *) etherrxbuff, length);
return 1;
}
#endif

49
fs/romfs/Makefile
View File

@ -1,49 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)libromfs.a
AOBJS =
COBJS = romfs.o
SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

240
fs/romfs/romfs.c
View File

@ -1,240 +0,0 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
#if defined(CONFIG_CMD_JFFS2)
#include <asm/byteorder.h>
#include <linux/stat.h>
#include <jffs2/jffs2.h>
#include <jffs2/load_kernel.h>
#undef DEBUG_ROMFS
/* ROMFS superblock */
struct romfs_super {
u32 word0;
u32 word1;
u32 size;
u32 checksum;
char name[0];
};
struct romfs_inode {
u32 next;
u32 spec;
u32 size;
u32 checksum;
char name[0];
};
extern flash_info_t flash_info[];
#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0])
#define ALIGN(x) (((x) & 0xfffffff0))
#define HEADERSIZE(name) (0x20 + ALIGN(strlen(name)))
static unsigned long romfs_resolve (unsigned long begin, unsigned long offset,
unsigned long size, int raw, char *filename)
{
unsigned long inodeoffset = 0, nextoffset;
struct romfs_inode *inode;
#ifdef DEBUG_ROMFS
printf ("ROMFS_resolve: begin 0x%x, offset 0x%x, size 0x%x, raw 0x%x, \
filename %s\n", begin, offset, size, raw, filename);
#endif
while (inodeoffset < size) {
inode = (struct romfs_inode *)(begin + offset + inodeoffset);
offset = 0;
nextoffset = ALIGN (inode->next);
#ifdef DEBUG_ROMFS
printf("inode 0x%x, name %s - len 0x%x, next inode 0x%x, \
compare names 0x%x\n",
inode, inode->name, strlen (inode->name), nextoffset,
strncmp (filename, inode->name, strlen (filename)));
#endif
if (!strncmp (filename, inode->name, strlen (inode->name))) {
char *p = strtok (NULL, "/");
if (raw && (p == NULL || *p == '\0')) {
return offset + inodeoffset;
}
return romfs_resolve (begin,
inodeoffset + HEADERSIZE (inode->name),
size, raw, p);
}
inodeoffset = nextoffset;
}
printf ("can't find corresponding entry\n");
return 0;
}
int romfs_load (char *loadoffset, struct part_info *info, char *filename)
{
struct romfs_inode *inode;
struct romfs_super *sb;
char *data;
int pocet;
sb = (struct romfs_super *) PART_OFFSET (info);
unsigned long offset;
offset = romfs_resolve (PART_OFFSET (info), HEADERSIZE (sb->name),
sb->size, 1, strtok (filename, "/"));
if (offset <= 0)
return offset;
inode = (struct romfs_inode *)(PART_OFFSET (info) + offset);
data = (char *)((int)inode + HEADERSIZE (inode->name));
pocet = inode->size;
while (pocet--) {
*loadoffset++ = *data++;
}
return inode->size;
}
static int romfs_list_inode (struct part_info *info, unsigned long offset)
{
struct romfs_inode *inode =
(struct romfs_inode *)(PART_OFFSET (info) + offset);
struct romfs_inode *hardlink = NULL;
char str[3], *data;
/*
* mapping spec.info means
* 0 hard link link destination [file header]
* 1 directory first file's header
* 2 regular file unused, must be zero [MBZ]
* 3 symbolic link unused, MBZ (file data is the link content)
* 4 block device 16/16 bits major/minor number
* 5 char device - " -
* 6 socket unused, MBZ
* 7 fifo unused, MBZ
*/
char attributes[] = "hdflbcsp";
str[0] = attributes[inode->next & 0x7];
str[1] = (inode->next & 0x8) ? 'x' : '-';
str[2] = '\0';
if ((str[0] == 'b') || (str[0] == 'c')) {
#ifdef DEBUG_ROMFS
printf (" %s %3d,%3d %12s 0x%08x 0x%08x", str,
(inode->spec & 0xffff0000) >> 16,
inode->spec & 0x0000ffff, inode->name, inode,
inode->spec);
#else
printf (" %s %3d,%3d %12s", str,
(inode->spec & 0xffff0000) >> 16,
inode->spec & 0x0000ffff);
#endif
} else {
#ifdef DEBUG_ROMFS
printf (" %s %7d %12s 0x%08x 0x%08x", str, inode->size,
inode->name, inode, inode->spec);
#else
printf (" %s %7d %12s", str, inode->size, inode->name);
#endif
if (str[0] == 'l') {
data = (char *)((int)inode + HEADERSIZE (inode->name));
puts (" -> ");
puts (data);
}
if (str[0] == 'h') {
hardlink = (struct romfs_inode *)(PART_OFFSET (info) +
inode->spec);
puts (" -> ");
puts (hardlink->name);
}
}
puts ("\n");
return ALIGN (inode->next);
}
int romfs_ls (struct part_info *info, char *filename)
{
struct romfs_inode *inode;
unsigned long inodeoffset = 0, nextoffset;
unsigned long offset, size;
struct romfs_super *sb;
sb = (struct romfs_super *)PART_OFFSET (info);
if (strlen (filename) == 0 || !strcmp (filename, "/")) {
offset = HEADERSIZE (sb->name);
size = sb->size;
} else {
offset = romfs_resolve (PART_OFFSET (info),
HEADERSIZE (sb->name), sb->size, 1,
strtok (filename, "/"));
if (offset == 0) {
return offset;
}
inode = (struct romfs_inode *)(PART_OFFSET (info) + offset);
if ((inode->next & 0x7) != 1) {
return (romfs_list_inode (info, offset) > 0);
}
size = sb->size;
offset = offset + HEADERSIZE (inode->name);
}
inodeoffset = offset + inodeoffset;
while (inodeoffset < size) {
nextoffset = romfs_list_inode (info, inodeoffset);
if (nextoffset == 0)
break;
inodeoffset = nextoffset;
}
return 1;
}
int romfs_info (struct part_info *info)
{
struct romfs_super *sb;
sb = (struct romfs_super *)PART_OFFSET (info);
printf ("name: \t\t%s, len %d B\n", sb->name, strlen (sb->name));
printf ("size of SB:\t%d B\n", HEADERSIZE (sb->name));
printf ("full size:\t%d B\n", sb->size);
printf ("checksum:\t0x%x\n", sb->checksum);
return 0;
}
int romfs_check (struct part_info *info)
{
struct romfs_super *sb;
if (info->dev->id->type != MTD_DEV_TYPE_NOR)
return 0;
sb = (struct romfs_super *)PART_OFFSET (info);
if ((sb->word0 != 0x2D726F6D) || (sb->word1 != 0x3166732D)) {
return 0;
}
return 1;
}
#endif