ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>utp
parent
d3daba10f1
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b5e01eecc8
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@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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configure_mr(nr, 0);
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
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configure_mr(nr, 1);
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configure_mr(nr, 0);
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configure_mr(nr, 1);
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}
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}
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}
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/**
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/**
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@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
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return 0;
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return 0;
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}
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}
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/*
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* Get SDRAM type connected to EMIF.
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* Assuming similar SDRAM parts are connected to both EMIF's
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* which is typically the case. So it is sufficient to get
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* SDRAM type from EMIF1.
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*/
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u32 emif_sdram_type()
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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return (readl(&emif->emif_sdram_config) &
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EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
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}
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static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
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static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
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{
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{
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u32 mr;
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u32 mr;
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@ -136,6 +136,14 @@
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#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
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#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
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#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
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#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
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#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
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#define DDR3_DATA0_IOCTRL_VALUE 0x84
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#define DDR3_DATA1_IOCTRL_VALUE 0x84
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#define DDR3_DATA2_IOCTRL_VALUE 0x84
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#define DDR3_DATA3_IOCTRL_VALUE 0x84
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/**
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/**
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* Configure DMM
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* Configure DMM
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*/
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*/
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@ -13,4 +13,16 @@
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#define AM33XX_GPIO2_BASE 0x481AC000
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#define AM33XX_GPIO2_BASE 0x481AC000
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#define AM33XX_GPIO3_BASE 0x481AE000
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#define AM33XX_GPIO3_BASE 0x481AE000
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#define GPIO_22 22
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/* GPIO CTRL register */
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#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
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#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
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#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
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/* GPIO OUTPUT ENABLE register */
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#define GPIO_OE_ENABLE(x) (1 << x)
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/* GPIO SETDATAOUT register */
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#define GPIO_SETDATAOUT(x) (1 << x)
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#endif /* _GPIO_AM33xx_H */
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#endif /* _GPIO_AM33xx_H */
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@ -1160,6 +1160,20 @@ static inline u32 get_emif_rev(u32 base)
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>> EMIF_REG_MAJOR_REVISION_SHIFT;
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>> EMIF_REG_MAJOR_REVISION_SHIFT;
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}
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}
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/*
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* Get SDRAM type connected to EMIF.
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* Assuming similar SDRAM parts are connected to both EMIF's
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* which is typically the case. So it is sufficient to get
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* SDRAM type from EMIF1.
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*/
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static inline u32 emif_sdram_type(void)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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return (readl(&emif->emif_sdram_config) &
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EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
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}
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/* assert macros */
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/* assert macros */
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#if defined(DEBUG)
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#if defined(DEBUG)
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#define emif_assert(c) ({ if (!(c)) for (;;); })
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#define emif_assert(c) ({ if (!(c)) for (;;); })
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@ -16,6 +16,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/gpio.h>
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#include <asm/emif.h>
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#include <asm/emif.h>
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#include "board.h"
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#include "board.h"
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@ -179,10 +180,70 @@ const u32 ext_phy_ctrl_const_base_lpddr2[] = {
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0x08102040
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0x08102040
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};
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};
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x0043,
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};
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const struct emif_regs ddr3_emif_regs_400Mhz = {
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.sdram_config = 0x638413B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0xEAAAD4DB,
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.sdram_tim2 = 0x266B7FDA,
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.sdram_tim3 = 0x107F8678,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E084008,
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_4 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_5 = 0x00400040,
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.emif_rd_wr_lvl_rmp_win = 0x0,
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.emif_rd_wr_lvl_rmp_ctl = 0x0,
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.emif_rd_wr_lvl_ctl = 0x0,
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.emif_rd_wr_exec_thresh = 0x00000405
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};
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const u32 ext_phy_ctrl_const_base_ddr3[] = {
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0x00400040,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x0,
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0x0,
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0x40000000,
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0x08102040
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};
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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{
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{
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*regs = ext_phy_ctrl_const_base_lpddr2;
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if (board_is_eposevm()) {
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
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*regs = ext_phy_ctrl_const_base_lpddr2;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
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} else if (board_is_gpevm()) {
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*regs = ext_phy_ctrl_const_base_ddr3;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
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}
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return;
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return;
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}
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}
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@ -280,9 +341,35 @@ void set_mux_conf_regs(void)
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enable_board_pin_mux();
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enable_board_pin_mux();
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}
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}
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static void enable_vtt_regulator(void)
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{
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u32 temp;
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/* enable module */
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writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
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/* enable output for GPIO0_22 */
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writel(GPIO_SETDATAOUT(GPIO_22),
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AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
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temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
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temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
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writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
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}
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void sdram_init(void)
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void sdram_init(void)
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{
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{
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config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
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/*
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* EPOS EVM has 1GB LPDDR2 connected to EMIF.
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* GP EMV has 1GB DDR3 connected to EMIF
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* along with VTT regulator.
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*/
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if (board_is_eposevm()) {
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config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
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} else if (board_is_gpevm()) {
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enable_vtt_regulator();
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config_ddr(0, &ioregs_ddr3, NULL, NULL,
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&ddr3_emif_regs_400Mhz, 0);
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}
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}
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}
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#endif
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#endif
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@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = {
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{-1},
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{-1},
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};
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};
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static struct module_pin_mux gpio0_22_pin_mux[] = {
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{OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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void enable_uart0_pin_mux(void)
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{
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{
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configure_module_pin_mux(uart0_pin_mux);
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configure_module_pin_mux(uart0_pin_mux);
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@ -42,6 +47,9 @@ void enable_board_pin_mux(void)
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{
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{
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configure_module_pin_mux(mmc0_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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configure_module_pin_mux(i2c0_pin_mux);
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configure_module_pin_mux(i2c0_pin_mux);
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if (board_is_gpevm())
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configure_module_pin_mux(gpio0_22_pin_mux);
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}
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}
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void enable_i2c0_pin_mux(void)
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void enable_i2c0_pin_mux(void)
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