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arm: Remove tx25 board 

This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
utp
Simon Glass 2015-08-30 19:19:39 -06:00 committed by Tom Rini
parent ad4f54ea86
commit b9599dd857
8 changed files with 0 additions and 524 deletions
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6
arch/arm/Kconfig
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@ -134,11 +134,6 @@ config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
config TARGET_TX25
bool "Support tx25"
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_ZMX25
bool "Support zmx25"
select CPU_ARM926EJS
@ -739,7 +734,6 @@ source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"

15
board/karo/tx25/Kconfig
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@ -1,15 +0,0 @@
if TARGET_TX25
config SYS_BOARD
default "tx25"
config SYS_VENDOR
default "karo"
config SYS_SOC
default "mx25"
config SYS_CONFIG_NAME
default "tx25"
endif

6
board/karo/tx25/MAINTAINERS
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@ -1,6 +0,0 @@
TX25 BOARD
M: John Rigby <jcrigby@gmail.com>
S: Maintained
F: board/karo/tx25/
F: include/configs/tx25.h
F: configs/tx25_defconfig

11
board/karo/tx25/Makefile
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@ -1,11 +0,0 @@
#
# (C) Copyright 2009 DENX Software Engineering
# Author: John Rigby <jcrigby@gmail.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
endif
obj-y += tx25.o

98
board/karo/tx25/lowlevel_init.S
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@ -1,98 +0,0 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on U-Boot and RedBoot sources for several different i.mx
* platforms.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/macro.h>
#include <asm/arch/macro.h>
.macro init_clocks
/*
* clocks
*
* first enable CLKO debug output
* 0x40000000 enables the debug CLKO signal
* 0x05000000 sets CLKO divider to 6
* 0x00600000 makes CLKO parent clk the USB clk
*/
write32 0x53f80064, 0x45600000
/* CCTL: ARM = 399 MHz, AHB = 133 MHz */
write32 0x53f80008, 0x20034000
/*
* PCDR2: NFC = 33.25 MHz
* This is required for the NAND Flash of this board, which is a Samsung
* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
* the NFC driver in symmetric (i.e. one-cycle) mode.
*/
write32 0x53f80020, 0x01010103
/*
* enable all implemented clocks in all three
* clock control registers
*/
write32 0x53f8000c, 0x1fffffff
write32 0x53f80010, 0xffffffff
write32 0x53f80014, 0xfdfff
.endm
.macro init_ddrtype
/*
* ddr_type is 3.3v SDRAM
*/
write32 0x43fac454, 0x800
.endm
/*
* sdram controller init
*/
.macro init_sdram_bank bankaddr, ctl, cfg
ldr r0, =0xb8001000
ldr r2, =\bankaddr
/*
* reset SDRAM controller
* then wait for initialization to complete
*/
ldr r1, =(1 << 1)
str r1, [r0, #0x10]
1: ldr r3, [r0, #0x10]
tst r3, #(1 << 31)
beq 1b
ldr r1, =0x95728
str r1, [r0, #\cfg] /* config */
ldr r1, =0x92116480 /* control | precharge */
str r1, [r0, #\ctl] /* write command to controller */
str r1, [r2, #0x400] /* command encoded in address */
ldr r1, =0xa2116480 /* auto refresh */
str r1, [r0, #\ctl]
ldrb r3, [r2] /* read dram twice to auto refresh */
ldrb r3, [r2]
ldr r1, =0xb2116480 /* control | load mode */
str r1, [r0, #\ctl] /* write command to controller */
strb r1, [r2, #0x33] /* command encoded in address */
ldr r1, =0x82116480 /* control | normal (0)*/
str r1, [r0, #\ctl] /* write command to controller */
.endm
.globl lowlevel_init
lowlevel_init:
init_aips
init_max
init_m3if
init_clocks
init_sdram_bank 0x80000000, 0x0, 0x4
init_sdram_bank 0x90000000, 0x8, 0xc
mov pc, lr

210
board/karo/tx25/tx25.c
View File

@ -1,210 +0,0 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on imx27lite.c:
* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
* And:
* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx25.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong bootflag)
{
/*
* copy ourselves from where we are running to where we were
* linked at. Use ulong pointers as all addresses involved
* are 4-byte-aligned.
*/
ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
for (dst = start_ptr; dst < end_ptr; dst++)
*dst = *(dst+(run_ptr-link_ptr));
/*
* branch to nand_boot's link-time address.
*/
asm volatile("ldr pc, =nand_boot");
}
#endif
#ifdef CONFIG_FEC_MXC
/*
* FIXME: need to revisit this
* The original code enabled PUE and 100-k pull-down without PKE, so the right
* value here is likely:
* 0 for no pull
* or:
* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
*/
#define FEC_OUT_PAD_CTRL 0
#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
void tx25_fec_init(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
};
static const iomux_v3_cfg_t fec_cfg_pads[] = {
MX25_PAD_FEC_RDATA0__GPIO_3_10,
MX25_PAD_FEC_RDATA1__GPIO_3_11,
MX25_PAD_FEC_RX_DV__GPIO_3_12,
};
debug("tx25_fec_init\n");
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* drop PHY power and assert reset (low) */
gpio_direction_output(GPIO_FEC_RESET_B, 0);
gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
mdelay(5);
debug("resetting phy\n");
/* turn on PHY power leaving reset asserted */
gpio_set_value(GPIO_FEC_ENABLE_B, 1);
mdelay(10);
/*
* Setup some strapping pins that are latched by the PHY
* as reset goes high.
*
* Set PHY mode to 111
* mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
* mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
* mode2 is tied high so nothing to do
*
* Turn on RMII mode
* RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
*/
/*
* set each mux mode to gpio mode
*/
imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
ARRAY_SIZE(fec_cfg_pads));
/*
* set each to 1 and make each an output
*/
gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
gpio_direction_output(IMX_GPIO_NR(3, 11), 1);
gpio_direction_output(IMX_GPIO_NR(3, 12), 1);
mdelay(22); /* this value came from RedBoot */
/*
* deassert PHY reset
*/
gpio_set_value(GPIO_FEC_RESET_B, 1);
mdelay(5);
/*
* set FEC pins back
*/
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#else
#define tx25_fec_init()
#endif
#ifdef CONFIG_MXC_UART
/*
* Set up input pins with hysteresis and 100-k pull-ups
*/
#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
/*
* FIXME: need to revisit this
* The original code enabled PUE and 100-k pull-down without PKE, so the right
* value here is likely:
* 0 for no pull
* or:
* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
*/
#define UART1_OUT_PAD_CTRL 0
static void tx25_uart1_init(void)
{
static const iomux_v3_cfg_t uart1_pads[] = {
NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#else
#define tx25_uart1_init()
#endif
int board_init()
{
tx25_uart1_init();
/* board id for linux */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int board_late_init(void)
{
tx25_fec_init();
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#else
#endif
}
int checkboard(void)
{
printf("KARO TX25\n");
return 0;
}

6
configs/tx25_defconfig
View File

@ -1,6 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_TX25=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

172
include/configs/tx25.h
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@ -1,172 +0,0 @@
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/*
* KARO TX25 board - SoC Configuration
*/
#define CONFIG_MX25
#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */
#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x810c0000
#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
#ifdef CONFIG_SPL_BUILD
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#else
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Memory Info
*/
/* malloc() len */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
/*
* Board has 2 32MB banks of DRAM but there is a bug when using
* both so only the first is configured
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x02000000
#if (CONFIG_NR_DRAM_BANKS == 2)
#define PHYS_SDRAM_2 0x90000000
#define PHYS_SDRAM_2_SIZE 0x02000000
#endif
/* 8MB DRAM test */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
/*
* Serial Info
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_MXC_GPIO
/*
* Flash & Environment
*/
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/* NAND */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
/* U-Boot general configuration */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print buffer sz */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
/* U-Boot commands */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
/*
* Ethernet
*/
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
#define CONFIG_MII
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 5
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"u-boot=tx25/u-boot.bin\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"hostname=tx25\0" \
"bootfile=tx25/uImage\0" \
"rootpath=/opt/eldk/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
"bootcmd=run net_nfs\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
"upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
#endif /* __CONFIG_H */