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ppc4xx: DDR/ECC: Use correct macros to clear error status 

Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.

Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.

Signed-off-by: Stefan Roese <sr@denx.de>
utp
Stefan Roese 2010-07-21 11:08:27 +02:00
parent 897d6abc50
commit b995d7cb2c
2 changed files with 22 additions and 1 deletions
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21
arch/powerpc/cpu/ppc4xx/ecc.c
View File

@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
/* clear ECC error repoting registers */
mtsdram(SDRAM_ECCES, 0xffffffff);
mtdcr(0x4c, 0xffffffff);
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
/*
* IBM DDR(1) core (440GX):
* Clear Mx bits in SDRAM0_BESR0/1
*/
mtsdram(SDRAM0_BESR0, 0xffffffff);
mtsdram(SDRAM0_BESR1, 0xffffffff);
#elif defined(CONFIG_440)
/*
* 440/460 DDR2 core:
* Clear EMID (Error PLB Master ID) in MQ0_ESL
*/
mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
#else
/*
* 405EX(r) DDR2 core:
* Clear M0ID (Error PLB Master ID) in SDRAM_BESR
*/
mtsdram(SDRAM_BESR, 0xf0000000);
#endif
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);

2
arch/powerpc/include/asm/ppc4xx-sdram.h
View File

@ -63,6 +63,8 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */