arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm code
v7_maint_dcache_all() does not work reliable when build with gcc6, see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788 While debugging this I learned that v7_maint_dcache_all() is unreliable when build with gcc5 too when it is marked as noinline. This commit fixes the reliability issues by replacing the C-code with the ready to use asm implementation from the kernel. Given that this code when written as C-code clearly is quite fragile (also see the existing comments about the C-code being the way it is to get optimal assembly) and that we have a proven asm alternative, I believe that this is the best solution. Note that we actually already had a copy of the kernel's v7_flush_dcache_all() before this commit in arch/arm/mach-uniphier/arm32/lowlevel_init.S. This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper which saves / restores the clobbered registers for use from C-code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>utp
Hans de Goede
Tom Rini
parent
456ecd08ec
commit
c09d29057a
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@ -7,7 +7,7 @@
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extra-y := start.o
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obj-y += cache_v7.o
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obj-y += cache_v7.o cache_v7_asm.o
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obj-y += cpu.o cp15.o
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obj-y += syslib.o
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@ -16,6 +16,10 @@
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Asm functions from cache_v7_asm.S */
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void v7_flush_dcache_all(void);
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static int check_cache_range(unsigned long start, unsigned long stop)
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{
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int ok = 1;
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@ -88,34 +92,6 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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DSB;
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}
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static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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* a. count down
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* b. have bigger loop inside
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*/
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for (way = num_ways - 1; way >= 0 ; way--) {
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for (set = num_sets - 1; set >= 0; set--) {
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setway = (level << 1) | (set << log2_line_len) |
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(way << way_shift);
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/*
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* Clean & Invalidate data/unified
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* cache line by set/way
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*/
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asm volatile (" mcr p15, 0, %0, c7, c14, 2"
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: : "r" (setway));
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}
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}
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/* DSB to make sure the operation is complete */
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DSB;
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}
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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{
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u32 ccsidr;
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@ -142,13 +118,8 @@ static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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log2_num_ways = log_2_n_round_up(num_ways);
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way_shift = (32 - log2_num_ways);
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if (operation == ARMV7_DCACHE_INVAL_ALL) {
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v7_inval_dcache_level_setway(level, num_sets, num_ways,
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v7_inval_dcache_level_setway(level, num_sets, num_ways,
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way_shift, log2_line_len);
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} else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
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v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
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way_shift, log2_line_len);
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}
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}
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static void v7_maint_dcache_all(u32 operation)
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@ -263,7 +234,7 @@ void invalidate_dcache_all(void)
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*/
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void flush_dcache_all(void)
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{
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v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
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v7_flush_dcache_all();
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v7_outer_cache_flush_all();
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}
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@ -0,0 +1,84 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <linux/sizes.h>
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#include <asm/system.h>
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#ifdef CONFIG_SYS_THUMB_BUILD
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#define ARM(x...)
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#define THUMB(x...) x
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#else
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#define ARM(x...) x
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#define THUMB(x...)
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#endif
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
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*/
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ENTRY(__v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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bx lr
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ENDPROC(__v7_flush_dcache_all)
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ENTRY(v7_flush_dcache_all)
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ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
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bl __v7_flush_dcache_all
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ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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bx lr
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ENDPROC(v7_flush_dcache_all)
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@ -38,7 +38,7 @@ ENTRY(lowlevel_init)
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* to do next is to create a page table and switch over to it.
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*/
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bl create_page_table
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bl v7_flush_dcache_all
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bl __v7_flush_dcache_all
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/* Disable MMU and Dcache before switching Page Table */
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
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@ -140,68 +140,3 @@ ENTRY(create_page_table)
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str r0, [r12, #4] @ mark the second section as Normal
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mov pc, lr
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ENDPROC(create_page_table)
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/* We don't use Thumb instructions for now */
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#define ARM(x...) x
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#define THUMB(x...)
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* - mm - mm_struct describing address space
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*
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* Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
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*/
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ENTRY(v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq finished @ if loc is 0, then no need to clean
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start_flush_levels:
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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mov pc, lr
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ENDPROC(v7_flush_dcache_all)
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