omap_gpmc: BCH8 support (ELM based)
This patch adds support for BCH8 error correction code to omap_gpmc driver. We use GPMC to generate codes/syndromes but we need ELM to find error locations from given syndrome. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> [ilya: merge it with omap_gpmc driver, some fixes and cleanup] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>utp
Mansoor Ahamed
Tom Rini
parent
04c3757829
commit
c3754e9cc2
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@ -29,6 +29,9 @@
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#include <linux/mtd/nand_ecc.h>
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#include <linux/compiler.h>
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#include <nand.h>
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#ifdef CONFIG_AM33XX
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#include <asm/arch/elm.h>
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#endif
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static uint8_t cs;
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static __maybe_unused struct nand_ecclayout hw_nand_oob =
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@ -234,6 +237,370 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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}
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}
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/*
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* BCH8 support (needs ELM and thus AM33xx-only)
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*/
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#ifdef CONFIG_AM33XX
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struct nand_bch_priv {
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uint8_t mode;
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uint8_t type;
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uint8_t nibbles;
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};
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/* bch types */
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#define ECC_BCH4 0
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#define ECC_BCH8 1
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#define ECC_BCH16 2
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/* BCH nibbles for diff bch levels */
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#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
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#define ECC_BCH4_NIBBLES 13
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#define ECC_BCH8_NIBBLES 26
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#define ECC_BCH16_NIBBLES 52
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static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
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static struct nand_bch_priv bch_priv = {
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.mode = NAND_ECC_HW_BCH,
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.type = ECC_BCH8,
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.nibbles = ECC_BCH8_NIBBLES
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};
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/*
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* omap_read_bch8_result - Read BCH result for BCH8 level
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*
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* @mtd: MTD device structure
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* @big_endian: When set read register 3 first
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* @ecc_code: Read syndrome from BCH result registers
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*/
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static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
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uint8_t *ecc_code)
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{
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uint32_t *ptr;
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int8_t i = 0, j;
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if (big_endian) {
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
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ecc_code[i++] = readl(ptr) & 0xFF;
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ptr--;
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = readl(ptr) & 0xFF;
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ptr--;
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}
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} else {
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ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
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for (j = 0; j < 3; j++) {
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
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ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
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ptr++;
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}
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ecc_code[i++] = readl(ptr) & 0xFF;
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ecc_code[i++] = 0; /* 14th byte is always zero */
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}
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}
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/*
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* omap_ecc_disable - Disable H/W ECC calculation
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*
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* @mtd: MTD device structure
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*
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*/
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static void omap_ecc_disable(struct mtd_info *mtd)
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{
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writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
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&gpmc_cfg->ecc_config);
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}
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/*
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* omap_rotate_ecc_bch - Rotate the syndrome bytes
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*
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* @mtd: MTD device structure
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* @calc_ecc: ECC read from ECC registers
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* @syndrome: Rotated syndrome will be retuned in this array
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*
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*/
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static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
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uint8_t *syndrome)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t n_bytes = 0;
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int8_t i, j;
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switch (bch->type) {
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case ECC_BCH4:
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n_bytes = 8;
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break;
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case ECC_BCH16:
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n_bytes = 28;
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break;
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case ECC_BCH8:
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default:
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n_bytes = 13;
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break;
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}
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for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
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syndrome[i] = calc_ecc[j];
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}
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/*
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* omap_calculate_ecc_bch - Read BCH ECC result
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*
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t big_endian = 1;
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int8_t ret = 0;
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if (bch->type == ECC_BCH8)
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omap_read_bch8_result(mtd, big_endian, ecc_code);
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else /* BCH4 and BCH16 currently not supported */
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ret = -1;
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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omap_ecc_disable(mtd);
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return ret;
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}
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/*
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* omap_fix_errors_bch - Correct bch error in the data
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*
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* @mtd: MTD device structure
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* @data: Data read from flash
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* @error_count:Number of errors in data
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* @error_loc: Locations of errors in the data
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*
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*/
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static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
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uint32_t error_count, uint32_t *error_loc)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t count = 0;
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uint32_t error_byte_pos;
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uint32_t error_bit_mask;
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uint32_t last_bit = (bch->nibbles * 4) - 1;
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/* Flip all bits as specified by the error location array. */
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/* FOR( each found error location flip the bit ) */
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for (count = 0; count < error_count; count++) {
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if (error_loc[count] > last_bit) {
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/* Remove the ECC spare bits from correction. */
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error_loc[count] -= (last_bit + 1);
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/* Offset bit in data region */
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error_byte_pos = ((512 * 8) -
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(error_loc[count]) - 1) / 8;
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/* Error Bit mask */
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error_bit_mask = 0x1 << (error_loc[count] % 8);
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/* Toggle the error bit to make the correction. */
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data[error_byte_pos] ^= error_bit_mask;
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}
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}
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}
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/*
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* omap_correct_data_bch - Compares the ecc read from nand spare area
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* with ECC registers values and corrects one bit error if it has occured
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*
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* @mtd: MTD device structure
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* @dat: page data
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* @read_ecc: ecc read from nand flash (ignored)
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* @calc_ecc: ecc read from ECC registers
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*
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* @return 0 if data is OK or corrected, else returns -1
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*/
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static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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struct nand_bch_priv *bch = chip->priv;
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uint8_t syndrome[28];
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uint32_t error_count = 0;
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uint32_t error_loc[8];
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uint32_t i, ecc_flag;
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ecc_flag = 0;
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for (i = 0; i < chip->ecc.bytes; i++)
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if (read_ecc[i] != 0xff)
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ecc_flag = 1;
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if (!ecc_flag)
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return 0;
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elm_reset();
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elm_config((enum bch_level)(bch->type));
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/*
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* while reading ECC result we read it in big endian.
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* Hence while loading to ELM we have rotate to get the right endian.
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*/
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omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
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/* use elm module to check for errors */
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if (elm_check_error(syndrome, bch->nibbles, &error_count,
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error_loc) != 0) {
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printf("ECC: uncorrectable.\n");
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return -1;
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}
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/* correct bch error */
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if (error_count > 0)
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omap_fix_errors_bch(mtd, dat, error_count, error_loc);
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return 0;
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}
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/*
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* omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
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* GPMC controller
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
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{
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uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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uint32_t unused_length = 0;
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struct nand_bch_priv *bch = chip->priv;
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switch (bch->nibbles) {
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case ECC_BCH4_NIBBLES:
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unused_length = 3;
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break;
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case ECC_BCH8_NIBBLES:
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unused_length = 2;
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break;
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case ECC_BCH16_NIBBLES:
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unused_length = 0;
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break;
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}
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/* Clear the ecc result registers, select ecc reg as 1 */
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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switch (mode) {
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case NAND_ECC_WRITE:
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/* eccsize1 config */
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val = ((unused_length + bch->nibbles) << 22);
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break;
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case NAND_ECC_READ:
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default:
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/* by default eccsize0 selected for ecc1resultsize */
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/* eccsize0 config */
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val = (bch->nibbles << 12);
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/* eccsize1 config */
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val |= (unused_length << 22);
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break;
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}
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/* ecc size configuration */
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writel(val, &gpmc_cfg->ecc_size_config);
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/* by default 512bytes sector page is selected */
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/* set bch mode */
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val = (1 << 16);
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/* bch4 / bch8 / bch16 */
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val |= (bch->type << 12);
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/* set wrap mode to 1 */
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val |= (1 << 8);
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val |= (dev_width << 7);
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val |= (cs << 1);
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writel(val, &gpmc_cfg->ecc_config);
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}
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/*
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* omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*
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*/
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static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
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{
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struct nand_chip *chip = mtd->priv;
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omap_hwecc_init_bch(chip, mode);
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/* enable ecc */
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writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
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}
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/**
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* omap_read_page_bch - hardware ecc based page read function
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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* @buf: buffer to store read data
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* @page: page number to read
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*
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*/
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static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page)
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{
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int i, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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uint8_t *ecc_calc = chip->buffers->ecccalc;
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uint8_t *ecc_code = chip->buffers->ecccode;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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uint8_t *oob = chip->oob_poi;
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uint32_t data_pos;
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uint32_t oob_pos;
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data_pos = 0;
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/* oob area start */
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oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
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oob += chip->ecc.layout->eccpos[0];
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
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oob += eccbytes) {
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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/* read data */
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
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chip->read_buf(mtd, p, eccsize);
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/* read respective ecc from oob area */
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
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chip->read_buf(mtd, oob, eccbytes);
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/* read syndrome */
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chip->ecc.calculate(mtd, p, &ecc_calc[i]);
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data_pos += eccsize;
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oob_pos += eccbytes;
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}
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for (i = 0; i < chip->ecc.total; i++)
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ecc_code[i] = chip->oob_poi[eccpos[i]];
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eccsteps = chip->ecc.steps;
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p = buf;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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int stat;
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stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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}
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return 0;
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}
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#endif /* CONFIG_AM33XX */
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#ifndef CONFIG_SPL_BUILD
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/*
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* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
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@ -269,7 +636,7 @@ void omap_nand_switch_ecc(int32_t hardware)
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nand->ecc.calculate = NULL;
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/* Setup the ecc configurations again */
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if (hardware) {
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if (hardware == 1) {
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_nand_oob;
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nand->ecc.size = 512;
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@ -279,6 +646,19 @@ void omap_nand_switch_ecc(int32_t hardware)
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nand->ecc.calculate = omap_calculate_ecc;
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omap_hwecc_init(nand);
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printf("HW ECC selected\n");
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#ifdef CONFIG_AM33XX
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} else if (hardware == 2) {
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_bch8_nand_oob;
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nand->ecc.size = 512;
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nand->ecc.bytes = 14;
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nand->ecc.read_page = omap_read_page_bch;
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nand->ecc.hwctl = omap_enable_ecc_bch;
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nand->ecc.correct = omap_correct_data_bch;
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nand->ecc.calculate = omap_calculate_ecc_bch;
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omap_hwecc_init_bch(nand, NAND_ECC_READ);
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printf("HW BCH8 selected\n");
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#endif
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} else {
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Use mtd default settings */
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@ -350,7 +730,27 @@ int board_nand_init(struct nand_chip *nand)
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nand->options |= NAND_BUSWIDTH_16;
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nand->chip_delay = 100;
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#ifdef CONFIG_AM33XX
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/* required in case of BCH */
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elm_init();
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/* BCH info that will be correct for SPL or overridden otherwise. */
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nand->priv = &bch_priv;
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#endif
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/* Default ECC mode */
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#ifdef CONFIG_AM33XX
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_bch8_nand_oob;
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nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
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nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
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nand->ecc.hwctl = omap_enable_ecc_bch;
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nand->ecc.correct = omap_correct_data_bch;
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nand->ecc.calculate = omap_calculate_ecc_bch;
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nand->ecc.read_page = omap_read_page_bch;
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omap_hwecc_init_bch(nand, NAND_ECC_READ);
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#else
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#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
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||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
#else
|
||||
|
|
@ -363,6 +763,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
nand->ecc.calculate = omap_calculate_ecc;
|
||||
omap_hwecc_init(nand);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
if (nand->options & NAND_BUSWIDTH_16)
|
||||
|
|
|
|||
Loading…
Reference in New Issue