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remarkable-uboot
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Merge remote-tracking branch 'u-boot-ti/master'

utp
Albert ARIBAUD 2012-10-26 07:00:28 +02:00
parent 186fc4db26 c7d35bef25
commit c68436fa42
47 changed files with 998 additions and 744 deletions
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1
arch/arm/cpu/armv7/am33xx/Makefile
View File

@ -21,6 +21,7 @@ COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
COBJS += mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))

239
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -36,9 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
static const struct gpio_bank gpio_bank_am33xx[4] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static struct am335x_baseboard_id __attribute__((section (".data"))) header;
static inline int board_is_bone(void)
{
return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
}
static inline int board_is_evm_sk(void)
{
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
return -EINVAL;
}
}
return 0;
}
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#endif
/*
* Determine what type of DDR we have.
*/
static short inline board_memory_type(void)
{
/* The following boards are known to use DDR3. */
if (board_is_evm_sk())
return EMIF_REG_SDRAM_TYPE_DDR3;
return EMIF_REG_SDRAM_TYPE_DDR2;
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
config_ddr(board_memory_type());
#endif
}
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
int cpu_mmc_init(bd_t *bis)
{
int ret;
ret = omap_mmc_init(0, 0, 0);
if (ret)
return ret;
@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
debug("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
else
return -1;
}
if (board_is_bone()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
return cpsw_register(&cpsw_data);
}
#endif

6
arch/arm/cpu/armv7/am33xx/clock.c
View File

@ -44,6 +44,7 @@
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
static void enable_interface_clocks(void)
{
@ -153,6 +154,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
/* RTC */
writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
;
}
static void mpu_pll_config(void)

1
arch/arm/cpu/armv7/am33xx/config.mk
View File

@ -13,6 +13,7 @@
#
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
else
ALL-y += $(obj)u-boot.img
endif

114
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@ -47,78 +47,6 @@ void dram_init_banksize(void)
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
.datauserank0delay = DDR2_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = DDR2_RATIO,
.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
.cmd0iclkout = DDR2_INVERT_CLKOUT,
.cmd1csratio = DDR2_RATIO,
.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
.cmd1iclkout = DDR2_INVERT_CLKOUT,
.cmd2csratio = DDR2_RATIO,
.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = DDR2_EMIF_SDCFG,
.ref_ctrl = DDR2_EMIF_SDREF,
.sdram_tim1 = DDR2_EMIF_TIM1,
.sdram_tim2 = DDR2_EMIF_TIM2,
.sdram_tim3 = DDR2_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
};
static const struct ddr_data ddr3_data = {
.datardsratio0 = DDR3_RD_DQS,
.datawdsratio0 = DDR3_WR_DQS,
.datafwsratio0 = DDR3_PHY_FIFO_WE,
.datawrsratio0 = DDR3_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = DDR3_RATIO,
.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
.cmd0iclkout = DDR3_INVERT_CLKOUT,
.cmd1csratio = DDR3_RATIO,
.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
.cmd1iclkout = DDR3_INVERT_CLKOUT,
.cmd2csratio = DDR3_RATIO,
.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
.cmd2iclkout = DDR3_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = DDR3_EMIF_SDCFG,
.ref_ctrl = DDR3_EMIF_SDREF,
.sdram_tim1 = DDR3_EMIF_TIM1,
.sdram_tim2 = DDR3_EMIF_TIM2,
.sdram_tim3 = DDR3_EMIF_TIM3,
.zq_config = DDR3_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
};
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@ -134,46 +62,26 @@ static void config_vtp(void)
;
}
void config_ddr(short ddr_type)
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs)
{
int ddr_pll, ioctrl_val;
const struct emif_regs *emif_regs;
const struct ddr_data *ddr_data;
const struct cmd_control *cmd_ctrl_data;
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
ddr_pll = 266;
cmd_ctrl_data = &ddr2_cmd_ctrl_data;
ddr_data = &ddr2_data;
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
ddr_pll = 303;
cmd_ctrl_data = &ddr3_cmd_ctrl_data;
ddr_data = &ddr3_data;
ioctrl_val = DDR3_IOCTRL_VALUE;
emif_regs = &ddr3_emif_reg_data;
} else {
puts("Unknown memory type");
hang();
}
enable_emif_clocks();
ddr_pll_config(ddr_pll);
ddr_pll_config(pll);
config_vtp();
config_cmd_ctrl(cmd_ctrl_data);
config_cmd_ctrl(ctrl);
config_ddr_data(0, ddr_data);
config_ddr_data(1, ddr_data);
config_ddr_data(0, data);
config_ddr_data(1, data);
config_io_ctrl(ioctrl_val);
config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
config_ddr_phy(emif_regs);
set_sdram_timings(emif_regs);
config_sdram(emif_regs);
config_ddr_phy(regs);
set_sdram_timings(regs);
config_sdram(regs);
}
#endif

33
arch/arm/cpu/armv7/am33xx/mux.c 100644
View File

@ -0,0 +1,33 @@
/*
* mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/mux.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
/*
* Configure the pin mux for the module
*/
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
{
int i;
if (!mod_pin_mux)
return;
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}

15
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -169,6 +169,12 @@ struct cm_dpll {
unsigned int clktimer2clk; /* offset 0x08 */
};
/* Control Module RTC registers */
struct cm_rtc {
unsigned int rtcclkctrl; /* offset 0x0 */
unsigned int clkstctrl; /* offset 0x4 */
};
/* Watchdog timer registers */
struct wd_timer {
unsigned int resv1[4];
@ -218,6 +224,15 @@ struct gptimer {
unsigned int tcar2; /* offset 0x58 */
};
/* RTC Registers */
struct rtc_regs {
unsigned int res[21];
unsigned int osc; /* offset 0x54 */
unsigned int res2[5];
unsigned int kick0r; /* offset 0x6c */
unsigned int kick1r; /* offset 0x70 */
};
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];

69
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -29,40 +29,41 @@
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
#define DDR2_EMIF_TIM1 0x0666B3C9
#define DDR2_EMIF_TIM2 0x243631CA
#define DDR2_EMIF_TIM3 0x0000033F
#define DDR2_EMIF_SDCFG 0x41805332
#define DDR2_EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0
#define DDR2_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00
#define DDR2_RD_DQS 0x12
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
#define DDR2_PHY_FIFO_WE 0x80
#define DDR2_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B
/* Micron MT47H128M16RT-25E */
#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
#define MT47H128M16RT25E_WR_DQS 0x00
#define MT47H128M16RT25E_PHY_WRLVL 0x00
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
#define DDR3_EMIF_READ_LATENCY 0x06
#define DDR3_EMIF_TIM1 0x0888A39B
#define DDR3_EMIF_TIM2 0x26337FDA
#define DDR3_EMIF_TIM3 0x501F830F
#define DDR3_EMIF_SDCFG 0x61C04AB2
#define DDR3_EMIF_SDREF 0x0000093B
#define DDR3_ZQ_CFG 0x50074BE4
#define DDR3_DLL_LOCK_DIFF 0x1
#define DDR3_RATIO 0x40
#define DDR3_INVERT_CLKOUT 0x1
#define DDR3_RD_DQS 0x3B
#define DDR3_WR_DQS 0x85
#define DDR3_PHY_WR_DATA 0xC1
#define DDR3_PHY_FIFO_WE 0x100
#define DDR3_IOCTRL_VALUE 0x18B
#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define MT41J128MJT125_RATIO 0x40
#define MT41J128MJT125_INVERT_CLKOUT 0x1
#define MT41J128MJT125_RD_DQS 0x3B
#define MT41J128MJT125_WR_DQS 0x85
#define MT41J128MJT125_PHY_WR_DATA 0xC1
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/**
* Configure SDRAM
@ -189,6 +190,8 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
void config_ddr(short ddr_type);
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs);
#endif /* _DDR_DEFS_H */

4
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -61,6 +61,7 @@
#define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
@ -83,4 +84,7 @@
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define AM335X_RTC_BASE 0x44E3E000
#endif /* __AM33XX_HARDWARE_H */

261
arch/arm/include/asm/arch-am33xx/mux.h 100644
View File

@ -0,0 +1,261 @@
/*
* mux.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MUX_H_
#define _MUX_H_
#include <common.h>
#include <asm/io.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int gpmc_ad0;
int gpmc_ad1;
int gpmc_ad2;
int gpmc_ad3;
int gpmc_ad4;
int gpmc_ad5;
int gpmc_ad6;
int gpmc_ad7;
int gpmc_ad8;
int gpmc_ad9;
int gpmc_ad10;
int gpmc_ad11;
int gpmc_ad12;
int gpmc_ad13;
int gpmc_ad14;
int gpmc_ad15;
int gpmc_a0;
int gpmc_a1;
int gpmc_a2;
int gpmc_a3;
int gpmc_a4;
int gpmc_a5;
int gpmc_a6;
int gpmc_a7;
int gpmc_a8;
int gpmc_a9;
int gpmc_a10;
int gpmc_a11;
int gpmc_wait0;
int gpmc_wpn;
int gpmc_be1n;
int gpmc_csn0;
int gpmc_csn1;
int gpmc_csn2;
int gpmc_csn3;
int gpmc_clk;
int gpmc_advn_ale;
int gpmc_oen_ren;
int gpmc_wen;
int gpmc_be0n_cle;
int lcd_data0;
int lcd_data1;
int lcd_data2;
int lcd_data3;
int lcd_data4;
int lcd_data5;
int lcd_data6;
int lcd_data7;
int lcd_data8;
int lcd_data9;
int lcd_data10;
int lcd_data11;
int lcd_data12;
int lcd_data13;
int lcd_data14;
int lcd_data15;
int lcd_vsync;
int lcd_hsync;
int lcd_pclk;
int lcd_ac_bias_en;
int mmc0_dat3;
int mmc0_dat2;
int mmc0_dat1;
int mmc0_dat0;
int mmc0_clk;
int mmc0_cmd;
int mii1_col;
int mii1_crs;
int mii1_rxerr;
int mii1_txen;
int mii1_rxdv;
int mii1_txd3;
int mii1_txd2;
int mii1_txd1;
int mii1_txd0;
int mii1_txclk;
int mii1_rxclk;
int mii1_rxd3;
int mii1_rxd2;
int mii1_rxd1;
int mii1_rxd0;
int rmii1_refclk;
int mdio_data;
int mdio_clk;
int spi0_sclk;
int spi0_d0;
int spi0_d1;
int spi0_cs0;
int spi0_cs1;
int ecap0_in_pwm0_out;
int uart0_ctsn;
int uart0_rtsn;
int uart0_rxd;
int uart0_txd;
int uart1_ctsn;
int uart1_rtsn;
int uart1_rxd;
int uart1_txd;
int i2c0_sda;
int i2c0_scl;
int mcasp0_aclkx;
int mcasp0_fsx;
int mcasp0_axr0;
int mcasp0_ahclkr;
int mcasp0_aclkr;
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
int ddr_a0;
int ddr_a1;
int ddr_a2;
int ddr_a3;
int ddr_a4;
int ddr_a5;
int ddr_a6;
int ddr_a7;
int ddr_a8;
int ddr_a9;
int ddr_a10;
int ddr_a11;
int ddr_a12;
int ddr_a13;
int ddr_a14;
int ddr_a15;
int ddr_odt;
int ddr_d0;
int ddr_d1;
int ddr_d2;
int ddr_d3;
int ddr_d4;
int ddr_d5;
int ddr_d6;
int ddr_d7;
int ddr_d8;
int ddr_d9;
int ddr_d10;
int ddr_d11;
int ddr_d12;
int ddr_d13;
int ddr_d14;
int ddr_d15;
int ddr_dqm0;
int ddr_dqm1;
int ddr_dqs0;
int ddr_dqsn0;
int ddr_dqs1;
int ddr_dqsn1;
int ddr_vref;
int ddr_vtp;
int ddr_strben0;
int ddr_strben1;
int ain7;
int ain6;
int ain5;
int ain4;
int ain3;
int ain2;
int ain1;
int ain0;
int vrefp;
int vrefn;
};
struct module_pin_mux {
short reg_offset;
unsigned char val;
};
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
(PAD_CTRL_BASE))->x)
/*
* Configure the pin mux for the module
*/
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
#endif

1
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -27,6 +27,7 @@
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF

27
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -19,24 +19,6 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
/*
* AM335x parts define a system EEPROM that defines certain sub-fields.
* We use these fields to in turn see what board we are on, and what
* that might require us to set or not set.
*/
#define HDR_NO_OF_MAC_ADDR 3
#define HDR_ETH_ALEN 6
#define HDR_NAME_LEN 8
struct am335x_baseboard_id {
unsigned int magic;
char name[HDR_NAME_LEN];
char version[4];
char serial[12];
char config[32];
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
#define BOARD_REV_ID 0x0
u32 get_cpu_rev(void);
@ -51,13 +33,4 @@ u32 get_device_type(void);
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif

1
arch/arm/include/asm/arch-omap3/dss.h
View File

@ -190,6 +190,7 @@ struct panel_config {
#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,

48
board/htkw/mcx/mcx.c
View File

@ -27,6 +27,8 @@
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/arch/dss.h>
#include <asm/arch/clocks.h>
#include "errno.h"
#include <i2c.h>
#ifdef CONFIG_USB_EHCI
@ -37,12 +39,16 @@
DECLARE_GLOBAL_DATA_PTR;
#define HOT_WATER_BUTTON 38
#define HOT_WATER_BUTTON 42
#define LCD_OUTPUT 55
/* Address of the framebuffer in RAM. */
#define FB_START_ADDRESS 0x88000000
#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
@ -67,6 +73,8 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
gpio_direction_output(LCD_OUTPUT, 0);
return 0;
}
@ -87,6 +95,7 @@ int board_late_init(void)
return 0;
setenv("bootcmd", "run swupdate");
return 0;
}
#endif
@ -109,15 +118,34 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_USB_EHCI_OMAP
#define USB_HOST_PWR_EN 132
int board_usb_init(void)
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct panel_config lcd_cfg = {
.timing_h = PANEL_TIMING_H(40, 40, 48),
.timing_v = PANEL_TIMING_V(29, 13, 3),
.pol_freq = 0x00003000, /* Pol Freq */
.divisor = 0x0001000E,
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
.lcd_size = PANEL_LCD_SIZE(800, 480),
};
int board_video_init(void)
{
if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
puts("Failed to get USB_HOST_PWR_EN pin\n");
return -ENODEV;
}
gpio_direction_output(USB_HOST_PWR_EN, 1);
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
void *fb;
fb = (void *)FB_START_ADDRESS;
lcd_cfg.frame_buffer = fb;
setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
omap3_dss_panel_config(&lcd_cfg);
omap3_dss_enable();
return 0;
}

30
board/htkw/mcx/mcx.h
View File

@ -96,7 +96,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
/* GPIO_43 LCD buffer enable */ \
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
@ -143,28 +143,28 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
@ -264,6 +264,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
/* GPIO_170 Touchscreen ISR */\
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
@ -313,11 +315,11 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \

8
board/teejet/mt_ventoux/mt_ventoux.c
View File

@ -45,6 +45,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define BUZZER 140
#define SPEAKER 141
#define USB1_PWR 127
#define USB2_PWR 149
#ifndef CONFIG_FPGA
#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
@ -247,6 +249,12 @@ int board_init(void)
gpio_direction_output(BUZZER, 0);
gpio_direction_output(SPEAKER, 0);
/* Activate USB power */
gpio_request(USB1_PWR, "USB1_PWR");
gpio_request(USB2_PWR, "USB2_PWR");
gpio_direction_output(USB1_PWR, 1);
gpio_direction_output(USB2_PWR, 1);
return 0;
}

1
board/ti/am335x/Makefile
View File

@ -22,6 +22,7 @@ ifdef CONFIG_SPL_BUILD
COBJS := mux.o
endif
COBJS += board.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

376
board/ti/am335x/board.c 100644
View File

@ -0,0 +1,376 @@
/*
* board.c
*
* Board functions for TI AM335X based boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
#ifdef CONFIG_SPL_BUILD
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static struct am335x_baseboard_id __attribute__((section (".data"))) header;
static inline int board_is_bone(void)
{
return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
}
static inline int board_is_bone_lt(void)
{
return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
}
static inline int board_is_evm_sk(void)
{
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
return -EINVAL;
}
}
return 0;
}
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
/*
* Unlock the RTC's registers. For more details please see the
* RTC_SS section of the TRM. In order to unlock we need to
* write these specific values (keys) in this order.
*/
writel(0x83e70b13, &rtc->kick0r);
writel(0x95a4f1e0, &rtc->kick1r);
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
}
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
(MT47H128M16RT25E_RD_DQS<<10) |
(MT47H128M16RT25E_RD_DQS<<0)),
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
(MT47H128M16RT25E_WR_DQS<<20) |
(MT47H128M16RT25E_WR_DQS<<10) |
(MT47H128M16RT25E_WR_DQS<<0)),
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
(MT47H128M16RT25E_PHY_WRLVL<<20) |
(MT47H128M16RT25E_PHY_WRLVL<<10) |
(MT47H128M16RT25E_PHY_WRLVL<<0)),
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = MT41J128MJT125_RATIO,
.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = MT41J128MJT125_RATIO,
.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
.zq_config = MT41J128MJT125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
};
#endif
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
debug("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
else
return -1;
}
if (board_is_bone() || board_is_bone_lt()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
return cpsw_register(&cpsw_data);
}
#endif

49
board/ti/am335x/board.h 100644
View File

@ -0,0 +1,49 @@
/*
* board.h
*
* TI AM335x boards information header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* TI AM335x parts define a system EEPROM that defines certain sub-fields.
* We use these fields to in turn see what board we are on, and what
* that might require us to set or not set.
*/
#define HDR_NO_OF_MAC_ADDR 3
#define HDR_ETH_ALEN 6
#define HDR_NAME_LEN 8
struct am335x_baseboard_id {
unsigned int magic;
char name[HDR_NAME_LEN];
char version[4];
char serial[12];
char config[32];
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif

250
board/ti/am335x/mux.c
View File

@ -16,242 +16,10 @@
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int gpmc_ad0;
int gpmc_ad1;
int gpmc_ad2;
int gpmc_ad3;
int gpmc_ad4;
int gpmc_ad5;
int gpmc_ad6;
int gpmc_ad7;
int gpmc_ad8;
int gpmc_ad9;
int gpmc_ad10;
int gpmc_ad11;
int gpmc_ad12;
int gpmc_ad13;
int gpmc_ad14;
int gpmc_ad15;
int gpmc_a0;
int gpmc_a1;
int gpmc_a2;
int gpmc_a3;
int gpmc_a4;
int gpmc_a5;
int gpmc_a6;
int gpmc_a7;
int gpmc_a8;
int gpmc_a9;
int gpmc_a10;
int gpmc_a11;
int gpmc_wait0;
int gpmc_wpn;
int gpmc_be1n;
int gpmc_csn0;
int gpmc_csn1;
int gpmc_csn2;
int gpmc_csn3;
int gpmc_clk;
int gpmc_advn_ale;
int gpmc_oen_ren;
int gpmc_wen;
int gpmc_be0n_cle;
int lcd_data0;
int lcd_data1;
int lcd_data2;
int lcd_data3;
int lcd_data4;
int lcd_data5;
int lcd_data6;
int lcd_data7;
int lcd_data8;
int lcd_data9;
int lcd_data10;
int lcd_data11;
int lcd_data12;
int lcd_data13;
int lcd_data14;
int lcd_data15;
int lcd_vsync;
int lcd_hsync;
int lcd_pclk;
int lcd_ac_bias_en;
int mmc0_dat3;
int mmc0_dat2;
int mmc0_dat1;
int mmc0_dat0;
int mmc0_clk;
int mmc0_cmd;
int mii1_col;
int mii1_crs;
int mii1_rxerr;
int mii1_txen;
int mii1_rxdv;
int mii1_txd3;
int mii1_txd2;
int mii1_txd1;
int mii1_txd0;
int mii1_txclk;
int mii1_rxclk;
int mii1_rxd3;
int mii1_rxd2;
int mii1_rxd1;
int mii1_rxd0;
int rmii1_refclk;
int mdio_data;
int mdio_clk;
int spi0_sclk;
int spi0_d0;
int spi0_d1;
int spi0_cs0;
int spi0_cs1;
int ecap0_in_pwm0_out;
int uart0_ctsn;
int uart0_rtsn;
int uart0_rxd;
int uart0_txd;
int uart1_ctsn;
int uart1_rtsn;
int uart1_rxd;
int uart1_txd;
int i2c0_sda;
int i2c0_scl;
int mcasp0_aclkx;
int mcasp0_fsx;
int mcasp0_axr0;
int mcasp0_ahclkr;
int mcasp0_aclkr;
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
int ddr_a0;
int ddr_a1;
int ddr_a2;
int ddr_a3;
int ddr_a4;
int ddr_a5;
int ddr_a6;
int ddr_a7;
int ddr_a8;
int ddr_a9;
int ddr_a10;
int ddr_a11;
int ddr_a12;
int ddr_a13;
int ddr_a14;
int ddr_a15;
int ddr_odt;
int ddr_d0;
int ddr_d1;
int ddr_d2;
int ddr_d3;
int ddr_d4;
int ddr_d5;
int ddr_d6;
int ddr_d7;
int ddr_d8;
int ddr_d9;
int ddr_d10;
int ddr_d11;
int ddr_d12;
int ddr_d13;
int ddr_d14;
int ddr_d15;
int ddr_dqm0;
int ddr_dqm1;
int ddr_dqs0;
int ddr_dqsn0;
int ddr_dqs1;
int ddr_dqsn1;
int ddr_vref;
int ddr_vtp;
int ddr_strben0;
int ddr_strben1;
int ain7;
int ain6;
int ain5;
int ain4;
int ain3;
int ain2;
int ain1;
int ain0;
int vrefp;
int vrefn;
};
struct module_pin_mux {
short reg_offset;
unsigned char val;
};
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
(PAD_CTRL_BASE))->x)
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
@ -362,20 +130,6 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
/*
* Configure the pin mux for the module
*/
static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
{
int i;
if (!mod_pin_mux)
return;
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);

11
drivers/spi/omap3_spi.c
View File

@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave)
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
* REVISIT: this controller could support SPI_3WIRE mode.
*/
#ifdef CONFIG_AM33XX
#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
/*
* The reference design on AM33xx has D0 and D1 wired up opposite
* of how it has been done on previous platforms. We assume that
* custom hardware will also follow this convention.
* Some boards have D0 wired as MOSI / D1 as MISO instead of
* The normal D0 as MISO / D1 as MOSI.
*/
conf &= OMAP3_MCSPI_CHCONF_DPE0;
conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
#else
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0;

11
drivers/usb/musb/musb_udc.c
View File

@ -640,8 +640,17 @@ static void musb_peri_ep0(void)
static void musb_peri_rx_ep(unsigned int ep)
{
u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
u16 peri_rxcount;
u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
if (debug_level > 0)
serial_printf("ERROR : %s %d without MUSB_RXCSR_RXPKTRDY set\n",
__PRETTY_FUNCTION__, ep);
return;
}
peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
if (peri_rxcount) {
struct usb_endpoint_instance *endpoint;
u32 length;

9
include/configs/am335x_evm.h
View File

@ -81,7 +81,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
@ -218,6 +218,13 @@
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/*

2
include/configs/am3517_crane.h
View File

@ -209,7 +209,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/am3517_evm.h
View File

@ -206,7 +206,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

14
include/configs/cm_t35.h
View File

@ -231,7 +231,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
@ -289,25 +289,15 @@
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#define CONFIG_ENV_IS_IN_NAND
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET

2
include/configs/devkit8000.h
View File

@ -233,7 +233,7 @@
"dhcp ${loadaddr}; " \
"run netargs; " \
"bootm ${loadaddr}\0" \
"autoboot=if mmc rescan ${mmcdev}; then " \
"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/igep00x0.h
View File

@ -180,7 +180,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"run importbootenv;" \

31
include/configs/mcx.h
View File

@ -115,8 +115,7 @@
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* commands to include */
@ -182,7 +181,7 @@
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
@ -256,22 +255,28 @@
"run nandargs; " \
"ubi part nand0,4;" \
"ubi readvol ${loadaddr} kernel;" \
"run addip addtty addmtd addfb addeth addmisc;" \
"run addtty addmtd addfb addeth addmisc;" \
"bootm ${loadaddr}\0" \
"swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\
"rootfstype=ubifs quiet loglevel=1 " \
"consoleblank=0 ${swupdate_misc}\0" \
"preboot=ubi part nand0,7;" \
"ubi readvol ${loadaddr} splash;" \
"bmp display ${loadaddr};" \
"gpio set 55\0" \
"swupdate_args=setenv bootargs root=/dev/ram " \
"quiet loglevel=1 " \
"consoleblank=0 ${swupdate_misc}\0" \
"swupdate=echo Running Sw-Update...;" \
"if printenv mtdparts;then echo Starting SwUpdate...; " \
"else mtdparts default;fi; " \
"ubi part nand0,5;" \
"ubi readvol 0x82000000 kernel_recovery;" \
"ubi part nand0,6;" \
"ubi readvol 0x84000000 fs_recovery;" \
"run swupdate_args; " \
"setenv bootargs ${bootargs} " \
"${mtdparts} " \
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
"omapdss.def_disp=lcd;" \
"bootm ${loadaddr}\0"
"bootm 0x82000000 0x84000000\0"
#define CONFIG_BOOTCOMMAND \
"run nandboot"
@ -302,6 +307,7 @@
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
#define CONFIG_PREBOOT
/*
* AM3517 has 12 GP timers, they can be driven by the system clock
@ -421,4 +427,13 @@
#define CONFIG_NET_RETRY_COUNT 10
#endif
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_OMAP3
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif /* __CONFIG_H */

2
include/configs/mx28evk.h
View File

@ -313,7 +313,7 @@
"dhcp ${uimage}; bootm\0"
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx51evk.h
View File

@ -182,7 +182,7 @@
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx53ard.h
View File

@ -119,7 +119,7 @@
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx53evk.h
View File

@ -132,7 +132,7 @@
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx53loco.h
View File

@ -140,7 +140,7 @@
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx53smd.h
View File

@ -118,7 +118,7 @@
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx6qarm2.h
View File

@ -106,7 +106,7 @@
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/mx6qsabrelite.h
View File

@ -164,7 +164,7 @@
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap3_beagle.h
View File

@ -289,7 +289,7 @@
"userbutton_nonxm=gpio input 7;\0"
/* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run userbutton; then " \
"setenv bootenv uEnv.txt;" \
"else " \

2
include/configs/omap3_evm.h
View File

@ -162,7 +162,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap3_logic.h
View File

@ -202,7 +202,7 @@
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"mmcdev=0\0" \
"autoboot=if mmc rescan ${mmcdev}; then " \
"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap3_overo.h
View File

@ -188,7 +188,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap3_zoom1.h
View File

@ -198,7 +198,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap4_common.h
View File

@ -165,7 +165,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/omap5_evm.h
View File

@ -167,7 +167,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

2
include/configs/tricorder.h
View File

@ -201,7 +201,7 @@
"run nandargs; " \
"run loaduimage_ubi; " \
"bootm ${loadaddr}\0" \
"autoboot=if mmc rescan ${mmcdev}; then " \
"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \

9
spl/Makefile
View File

@ -112,16 +112,13 @@ LDPPFLAGS += \
$(shell $(LD) --version | \
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
ifdef CONFIG_OMAP
$(OBJTREE)/MLO: $(obj)u-boot-spl.bin
$(OBJTREE)/tools/mkimage -T omapimage \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
endif
ifdef CONFIG_AM33XX
$(OBJTREE)/MLO: $(obj)u-boot-spl.bin
$(OBJTREE)/tools/mkimage -T omapimage \
$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin
$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
endif
ALL-y += $(obj)u-boot-spl.bin

83
tools/omapimage.c
View File

@ -42,6 +42,18 @@
#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header))
#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE)
static int do_swap32 = 0;
static uint32_t omapimage_swap32(uint32_t data)
{
uint32_t result = 0;
result = (data & 0xFF000000) >> 24;
result |= (data & 0x00FF0000) >> 8;
result |= (data & 0x0000FF00) << 8;
result |= (data & 0x000000FF) << 24;
return result;
}
static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE];
static int omapimage_check_image_types(uint8_t type)
@ -80,12 +92,17 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size,
{
struct ch_toc *toc = (struct ch_toc *)ptr;
struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
uint32_t offset, size;
uint32_t offset, size, gph_size, gph_load_addr;
while (toc->section_offset != 0xffffffff
&& toc->section_size != 0xffffffff) {
offset = toc->section_offset;
size = toc->section_size;
if (do_swap32) {
offset = omapimage_swap32(toc->section_offset);
size = omapimage_swap32(toc->section_size);
} else {
offset = toc->section_offset;
size = toc->section_size;
}
if (!offset || !size)
return -1;
if (offset >= OMAP_CH_HDR_SIZE ||
@ -93,9 +110,18 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size,
return -1;
toc++;
}
if (!valid_gph_size(gph->size))
if (do_swap32) {
gph_size = omapimage_swap32(gph->size);
gph_load_addr = omapimage_swap32(gph->load_addr);
} else {
gph_size = gph->size;
gph_load_addr = gph->load_addr;
}
if (!valid_gph_size(gph_size))
return -1;
if (!valid_gph_load_addr(gph->load_addr))
if (!valid_gph_load_addr(gph_load_addr))
return -1;
return 0;
@ -128,12 +154,17 @@ static void omapimage_print_header(const void *ptr)
const struct ch_toc *toc = (struct ch_toc *)ptr;
const struct gp_header *gph =
(struct gp_header *)(ptr+OMAP_CH_HDR_SIZE);
uint32_t offset, size;
uint32_t offset, size, gph_size, gph_load_addr;
while (toc->section_offset != 0xffffffff
&& toc->section_size != 0xffffffff) {
offset = toc->section_offset;
size = toc->section_size;
if (do_swap32) {
offset = omapimage_swap32(toc->section_offset);
size = omapimage_swap32(toc->section_size);
} else {
offset = toc->section_offset;
size = toc->section_size;
}
if (offset >= OMAP_CH_HDR_SIZE ||
offset+size >= OMAP_CH_HDR_SIZE)
@ -148,22 +179,26 @@ static void omapimage_print_header(const void *ptr)
toc++;
}
if (!valid_gph_size(gph->size)) {
fprintf(stderr,
"Error: invalid image size %x\n",
gph->size);
if (do_swap32) {
gph_size = omapimage_swap32(gph->size);
gph_load_addr = omapimage_swap32(gph->load_addr);
} else {
gph_size = gph->size;
gph_load_addr = gph->load_addr;
}
if (!valid_gph_size(gph_size)) {
fprintf(stderr, "Error: invalid image size %x\n", gph_size);
exit(EXIT_FAILURE);
}
if (!valid_gph_load_addr(gph->load_addr)) {
fprintf(stderr,
"Error: invalid image load address %x\n",
gph->size);
if (!valid_gph_load_addr(gph_load_addr)) {
fprintf(stderr, "Error: invalid image load address %x\n",
gph_load_addr);
exit(EXIT_FAILURE);
}
printf("GP Header: Size %x LoadAddr %x\n",
gph->size, gph->load_addr);
printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr);
}
static int toc_offset(void *hdr, void *member)
@ -194,6 +229,18 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd,
gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE;
gph->load_addr = params->addr;
if (strncmp(params->imagename, "byteswap", 8) == 0) {
do_swap32 = 1;
int swapped = 0;
uint32_t *data = (uint32_t *)ptr;
while (swapped <= (sbuf->st_size / sizeof(uint32_t))) {
*data = omapimage_swap32(*data);
swapped++;
data++;
}
}
}
int omapimage_check_params(struct mkimage_params *params)