MLK-18591-12 android: iot: Add board support imx6ul nxpu board
Porting the board support for imx6ul nxpu iopb board from v2017.03 Signed-off-by: Ye Li <ye.li@nxp.com>zero-sugar
Ye Li
parent
1b60a63576
commit
c7219c08b7
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@ -428,6 +428,13 @@ config TARGET_MX6UL_14X14_LPDDR2_ARM2
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select DM
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select DM_THERMAL
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config TARGET_MX6UL_NXPU_IOPB
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bool "Support mx6ul_nxpu_iopb"
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select BOARD_LATE_INIT
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select MX6UL
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select DM
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select DM_THERMAL
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config TARGET_MX6UL_ENGICAM
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bool "Support Engicam GEAM6UL/Is.IoT"
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select BOARD_LATE_INIT
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@ -628,6 +635,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
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source "board/freescale/mx6sxsabreauto/Kconfig"
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source "board/freescale/mx6sx_17x17_arm2/Kconfig"
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source "board/freescale/mx6sx_19x19_arm2/Kconfig"
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source "board/freescale/mx6ul_nxpu_iopb/Kconfig"
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source "board/freescale/mx6ul_14x14_evk/Kconfig"
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source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
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source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
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@ -0,0 +1,15 @@
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if TARGET_MX6UL_NXPU_IOPB
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config SYS_BOARD
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default "mx6ul_nxpu_iopb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "mx6ul_nxpu_iopb"
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endif
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@ -0,0 +1,6 @@
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MX6ULIOPB BOARD
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M: Fang Hui <hui.fang@nxp.com>
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S: Maintained
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F: board/freescale/mx6ul_nxpu_iopb/
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F: include/configs/mx6ul_nxpu_iopb.h
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F: configs/mx6ul_nxpu_iopb_defconfig
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@ -0,0 +1,6 @@
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# (C) Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6ul_nxpu_iopb.o
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@ -0,0 +1,188 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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#ifdef CONFIG_QSPI_BOOT
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BOOT_FROM qspi
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#elif defined(CONFIG_NOR_BOOT)
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BOOT_FROM nor
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#else
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BOOT_FROM sd
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#endif
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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#ifdef CONFIG_DDR3L_MT41K256M16HA
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/* DDR type MT41K256M16HA-125 which is EOL */
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E04B4 0x000C0000
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DATA 4 0x020E04AC 0x00000000
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DATA 4 0x020E027C 0x00000030
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DATA 4 0x020E0250 0x00000030
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DATA 4 0x020E024C 0x00000030
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DATA 4 0x020E0490 0x00000030
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DATA 4 0x020E0288 0x00000030
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DATA 4 0x020E0270 0x00000000
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DATA 4 0x020E0260 0x00000030
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DATA 4 0x020E0264 0x00000030
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DATA 4 0x020E04A0 0x00000030
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DATA 4 0x020E0494 0x00020000
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DATA 4 0x020E0280 0x00000030
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DATA 4 0x020E0284 0x00000030
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DATA 4 0x020E04B0 0x00020000
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DATA 4 0x020E0498 0x00000030
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DATA 4 0x020E04A4 0x00000030
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DATA 4 0x020E0244 0x00000030
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DATA 4 0x020E0248 0x00000030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B080C 0x00000000
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DATA 4 0x021B083C 0x41490145
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DATA 4 0x021B0848 0x40404546
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DATA 4 0x021B0850 0x4040524D
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B08C0 0x00921012
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x0002002D
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DATA 4 0x021B0008 0x00333030
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DATA 4 0x021B000C 0x676B52F3
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DATA 4 0x021B0010 0xB66D8B63
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DATA 4 0x021B0014 0x01FF00DB
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DATA 4 0x021B0018 0x00201740
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B002C 0x000026D2
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DATA 4 0x021B0030 0x006B1023
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DATA 4 0x021B0040 0x0000004F
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DATA 4 0x021B0000 0x84180000
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DATA 4 0x021B001C 0x02008032
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DATA 4 0x021B001C 0x00008033
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DATA 4 0x021B001C 0x00048031
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DATA 4 0x021B001C 0x15208030
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DATA 4 0x021B001C 0x04008040
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DATA 4 0x021B0020 0x00000800
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DATA 4 0x021B0818 0x00000227
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DATA 4 0x021B0004 0x0002552D
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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#else
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/* New DDR type MT41K256M16TW-107 */
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E04B4 0x000C0000
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DATA 4 0x020E04AC 0x00000000
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DATA 4 0x020E027C 0x00000030
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DATA 4 0x020E0250 0x00000030
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DATA 4 0x020E024C 0x00000030
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DATA 4 0x020E0490 0x00000030
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DATA 4 0x020E0288 0x00000030
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DATA 4 0x020E0270 0x00000000
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DATA 4 0x020E0260 0x00000030
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DATA 4 0x020E0264 0x00000030
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DATA 4 0x020E04A0 0x00000030
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DATA 4 0x020E0494 0x00020000
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DATA 4 0x020E0280 0x00000030
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DATA 4 0x020E0284 0x00000030
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DATA 4 0x020E04B0 0x00020000
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DATA 4 0x020E0498 0x00000030
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DATA 4 0x020E04A4 0x00000030
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DATA 4 0x020E0244 0x00000030
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DATA 4 0x020E0248 0x00000030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B080C 0x00000000
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DATA 4 0x021B083C 0x41570155
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DATA 4 0x021B0848 0x4040474A
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DATA 4 0x021B0850 0x40405550
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B08C0 0x00921012
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x0002002D
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DATA 4 0x021B0008 0x1B333030
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DATA 4 0x021B000C 0x676B52F3
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DATA 4 0x021B0010 0xB66D0B63
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DATA 4 0x021B0014 0x01FF00DB
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DATA 4 0x021B0018 0x00201740
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B002C 0x000026D2
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DATA 4 0x021B0030 0x006B1023
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DATA 4 0x021B0040 0x0000004F
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DATA 4 0x021B0000 0x84180000
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DATA 4 0x021B0890 0x23400A38
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DATA 4 0x021B001C 0x02008032
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DATA 4 0x021B001C 0x00008033
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DATA 4 0x021B001C 0x00048031
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DATA 4 0x021B001C 0x15208030
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DATA 4 0x021B001C 0x04008040
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DATA 4 0x021B0020 0x00000800
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DATA 4 0x021B0818 0x00000227
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DATA 4 0x021B0004 0x0002552D
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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#endif
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#endif
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@ -0,0 +1,546 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <linux/sizes.h>
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#include <linux/fb.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <mxsfb.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#ifdef CONFIG_POWER
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../common/pfuze.h"
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#endif
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#ifdef CONFIG_FSL_FASTBOOT
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#include <fsl_fastboot.h>
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#ifdef CONFIG_ANDROID_RECOVERY
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#include <recovery.h>
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#endif
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#endif /*CONFIG_FSL_FASTBOOT*/
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | \
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PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC and EEPROM */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
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.gp = IMX_GPIO_NR(1, 2),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
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.gp = IMX_GPIO_NR(1, 3),
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},
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};
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#endif
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int dram_init(void)
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{
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#ifdef CONFIG_IMX_TRUSTY_OS
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gd->ram_size = PHYS_SDRAM_SIZE - TRUSTY_OS_RAM_SIZE;
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#else
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gd->ram_size = PHYS_SDRAM_SIZE;
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#endif
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return 0;
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}
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static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* RST_B */
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
/* CD */
|
||||
MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
/*
|
||||
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
|
||||
* be used for ENET1 or ENET2, cannot be used for both.
|
||||
*/
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), /* MDIO */
|
||||
MX6_PAD_ENET2_RX_DATA1__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), /* MDC */
|
||||
|
||||
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
||||
MX6_PAD_LCD_HSYNC__GPIO3_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
|
||||
MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(int fec_id)
|
||||
{
|
||||
if (fec_id == 0)
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
else
|
||||
printf("Warning: fec_id %d, should be 0\n", fec_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17)
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
|
||||
dev_no = 1;
|
||||
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(int fec_id)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
if (0 == fec_id) {
|
||||
if (check_module_fused(MX6_MODULE_ENET1))
|
||||
return -1;
|
||||
|
||||
/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[17](ENET1_TX_CLK),
|
||||
set gpr1[13](ENET1_CLK_SEL) */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
||||
IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
|
||||
} else {
|
||||
if (check_module_fused(MX6_MODULE_ENET2))
|
||||
return -1;
|
||||
|
||||
/* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
|
||||
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
|
||||
}
|
||||
|
||||
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
enable_enet_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
/*
|
||||
* Leave it here, but default configuration only supports 1 port now,
|
||||
* because we need sd1 and i2c1
|
||||
*/
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* At default the 3v3 enables the MIC2026 for VBUS power */
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
|
||||
ARRAY_SIZE(usb_otg1_pads));
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
|
||||
ARRAY_SIZE(usb_otg2_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
unsigned int reg, rev_id;
|
||||
|
||||
ret = power_pfuze3000_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pfuze = pmic_get("PFUZE3000");
|
||||
ret = pmic_probe(pfuze);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
|
||||
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1B step ramp up time from 2us to 4us/25mV */
|
||||
reg = 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
|
||||
|
||||
/* SW1B mode to APS/PFM */
|
||||
reg = 0xc;
|
||||
pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
u32 vddarm;
|
||||
|
||||
struct pmic *p = pfuze;
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
|
||||
value &= ~0x1f;
|
||||
value |= PFUZE300_SW1AB_SETP(1275);
|
||||
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
|
||||
|
||||
set_anatop_bypass(1);
|
||||
vddarm = PFUZE300_SW1AB_SETP(1175);
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
|
||||
value &= ~0x1f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
gpio_request(IMX_GPIO_NR(3, 2), "reset_gpio");
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 2) , 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 2) , 1);
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec(CONFIG_FEC_ENET_DEV);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
setup_usb();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6UL NXPU IOPB\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_FASTBOOT
|
||||
#ifdef CONFIG_ANDROID_RECOVERY
|
||||
int is_recovery_key_pressing(void)
|
||||
{
|
||||
/* No key defined for this board */
|
||||
return 0;
|
||||
}
|
||||
#endif /*CONFIG_ANDROID_RECOVERY*/
|
||||
#endif /*CONFIG_FSL_FASTBOOT*/
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6ul_ddr3_iopb_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x000C0000
|
||||
str r1, [r0, #0x4B4]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x4AC]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x27C]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x250]
|
||||
str r1, [r0, #0x24C]
|
||||
str r1, [r0, #0x490]
|
||||
str r1, [r0, #0x288]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x270]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x260]
|
||||
str r1, [r0, #0x264]
|
||||
str r1, [r0, #0x4A0]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x494]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x280]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x284]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x4B0]
|
||||
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x498]
|
||||
str r1, [r0, #0x4A4]
|
||||
str r1, [r0, #0x244]
|
||||
str r1, [r0, #0x248]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x1C]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x80C]
|
||||
ldr r1, =0x41570155
|
||||
str r1, [r0, #0x83C]
|
||||
ldr r1, =0x4040474A
|
||||
str r1, [r0, #0x848]
|
||||
ldr r1, =0x40405550
|
||||
str r1, [r0, #0x850]
|
||||
ldr r1, =0x33333333
|
||||
str r1, [r0, #0x81C]
|
||||
str r1, [r0, #0x820]
|
||||
ldr r1, =0xF3333333
|
||||
str r1, [r0, #0x82C]
|
||||
str r1, [r0, #0x830]
|
||||
ldr r1, =0x00921012
|
||||
str r1, [r0, #0x8C0]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8B8]
|
||||
ldr r1, =0x0002002D
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x1B333030
|
||||
str r1, [r0, #0x008]
|
||||
ldr r1, =0x676B52F3
|
||||
str r1, [r0, #0x00C]
|
||||
ldr r1, =0xB66D0B63
|
||||
str r1, [r0, #0x010]
|
||||
ldr r1, =0x01FF00DB
|
||||
str r1, [r0, #0x014]
|
||||
ldr r1, =0x00201740
|
||||
str r1, [r0, #0x018]
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x000026D2
|
||||
str r1, [r0, #0x02C]
|
||||
ldr r1, =0x006B1023
|
||||
str r1, [r0, #0x030]
|
||||
ldr r1, =0x0000004F
|
||||
str r1, [r0, #0x040]
|
||||
ldr r1, =0x84180000
|
||||
str r1, [r0, #0x000]
|
||||
ldr r1, =0x23400A38
|
||||
str r1, [r0, #0x890]
|
||||
ldr r1, =0x02008032
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00008033
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00048031
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x15208030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04008040
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x020]
|
||||
ldr r1, =0x00000227
|
||||
str r1, [r0, #0x818]
|
||||
ldr r1, =0x0002552D
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00011006
|
||||
str r1, [r0, #0x404]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x01C]
|
||||
.endm
|
||||
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #0x68]
|
||||
str r1, [r0, #0x6C]
|
||||
str r1, [r0, #0x70]
|
||||
str r1, [r0, #0x74]
|
||||
str r1, [r0, #0x78]
|
||||
str r1, [r0, #0x7C]
|
||||
str r1, [r0, #0x80]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
imx6ul_ddr3_iopb_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_TARGET_MX6UL_NXPU_IOPB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_BOOTDELAY=-2
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_AVB_ATX=y
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT,ARMV7_NONSEC"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_IMX_TRUSTY_OS=y
|
||||
CONFIG_AVB_ATX=y
|
||||
CONFIG_TARGET_MX6UL_NXPU_IOPB=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_BOOTDELAY=-2
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6UL NXPU IOPB board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __MX6UL_NXPU_IOPB_CONFIG_H
|
||||
#define __MX6UL_NXPU_IOPB_CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
#if !defined(CONFIG_MX6UL_9X9_LPDDR2)
|
||||
/* DCDC used on 14x14 EVK, no PMIC */
|
||||
#undef CONFIG_LDO_BYPASS_CHECK
|
||||
#endif
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART3_BASE
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_USDHC
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_ENET_DEV 0
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#define CONFIG_FEC_XCV_TYPE MII100
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_PHYLIB
|
||||
#endif
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#endif
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_512M
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE3000
|
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
|
||||
|
||||
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#if defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"panel=TFT43AB\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"panel=TFT43AB\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc2\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR
|
||||
#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (13 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET (60 << 20)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
#define CONFIG_MODULE_FUSE
|
||||
#define CONFIG_OF_SYSTEM_SETUP
|
||||
|
||||
#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
|
||||
#include "mx6ul_nxpu_iopb_android_things.h"
|
||||
#endif
|
||||
|
||||
|
||||
#define PRODUCT_NAME "imx6ul"
|
||||
#define VARIANT_NAME "imx6ul_iopb"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
|
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX6UL_NXPU_IOPB_ANDROID_THINGS_H
|
||||
#define __MX6UL_NXPU_IOPB_ANDROID_THINGS_H
|
||||
#include "mx_android_common.h"
|
||||
#define TRUSTY_OS_ENTRY 0x9e000000
|
||||
#define TRUSTY_OS_RAM_SIZE 0x2000000
|
||||
#define TRUSTY_OS_MMC_BLKS 0xFFF
|
||||
#define TEE_HWPARTITION_ID 2
|
||||
|
||||
#define AVB_RPMB
|
||||
#ifdef AVB_RPMB
|
||||
#define KEYSLOT_BLKS 0xFFF
|
||||
#define KEYSLOT_HWPARTITION_ID 2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AVB_ATX
|
||||
#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMX_TRUSTY_OS
|
||||
#define NON_SECURE_FASTBOOT
|
||||
#define TRUSTY_KEYSLOT_PACKAGE
|
||||
#endif
|
||||
|
||||
/* For NAND we don't support lock/unlock */
|
||||
#ifndef CONFIG_NAND_BOOT
|
||||
#define CONFIG_FASTBOOT_LOCK
|
||||
#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
|
||||
#define FSL_FASTBOOT_FB_DEV "mmc"
|
||||
#endif
|
||||
|
||||
#define CONFIG_ANDROID_AB_SUPPORT
|
||||
#define CONFIG_SYSTEM_RAMDISK_SUPPORT
|
||||
#define CONFIG_FSL_CAAM_KB
|
||||
#define CONFIG_CMD_FSL_CAAM_KB
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
|
||||
#define CONFIG_AVB_SUPPORT
|
||||
#ifdef CONFIG_AVB_SUPPORT
|
||||
#ifdef CONFIG_SYS_MALLOC_LEN
|
||||
#undef CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
#endif
|
||||
#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
/* fuse bank size in word */
|
||||
#define CONFIG_AVB_FUSE_BANK_SIZEW 8
|
||||
#define CONFIG_AVB_FUSE_BANK_START 10
|
||||
#define CONFIG_AVB_FUSE_BANK_END 15
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* __MX6UL_NXPU_IOPB_ANDROID_THINGS_H */
|
||||
Loading…
Reference in New Issue