mpc8xx: remove rbc823 board support
This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>utp
Masahiro Yamada
Tom Rini
parent
0657e46e28
commit
c750b9c012
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = rbc823.o flash.o kbd.o
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@ -1,445 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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/*
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* Functions
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*/
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static ulong flash_get_size(vu_long *addr, flash_info_t *info);
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static int write_word(flash_info_t *info, ulong dest, ulong data);
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static void flash_get_offsets(ulong base, flash_info_t *info);
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unsigned long flash_init(void)
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{
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unsigned long size_b0;
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int i;
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/* Init: no FLASHes known */
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
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flash_info[i].flash_id = FLASH_UNKNOWN;
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/* Detect size */
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
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&flash_info[0]);
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/* Setup offsets */
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flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* Monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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#endif
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flash_info[0].size = size_b0;
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return size_b0;
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}
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/*-----------------------------------------------------------------------
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* Fix this to support variable sector sizes
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*/
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static void flash_get_offsets(ulong base, flash_info_t *info)
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{
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int i;
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/* set up sector start address table */
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if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
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/* set sector offsets for bottom boot block type */
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for (i = 0; i < info->sector_count; i++)
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info->start[i] = base + (i * 0x00010000);
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}
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info(flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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puts("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf("AMD ");
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break;
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case FLASH_MAN_FUJ:
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printf("FUJITSU ");
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break;
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case FLASH_MAN_BM:
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printf("BRIGHT MICRO ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM040:
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printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
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break;
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case FLASH_AM400B:
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printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM400T:
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printf("AM29LV400T (4 Mbit, top boot sector)\n");
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break;
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case FLASH_AM800B:
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printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM800T:
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printf("AM29LV800T (8 Mbit, top boot sector)\n");
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break;
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case FLASH_AM160B:
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printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T:
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printf("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320B:
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printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM320T:
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printf("AM29LV320T (32 Mbit, top boot sector)\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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break;
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}
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if (info->size >> 20) {
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printf(" Size: %ld MB in %d Sectors\n",
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info->size >> 20,
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info->sector_count);
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} else {
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printf(" Size: %ld KB in %d Sectors\n",
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info->size >> 10,
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info->sector_count);
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}
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puts(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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puts("\n ");
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printf(" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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putc('\n');
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size(vu_long *addr, flash_info_t *info)
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{
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short i;
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volatile unsigned char *caddr;
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char value;
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caddr = (volatile unsigned char *)addr ;
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/* Write auto select command: read Manufacturer ID */
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debug("Base address is: %8p\n", caddr);
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caddr[0x0555] = 0xAA;
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caddr[0x02AA] = 0x55;
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caddr[0x0555] = 0x90;
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value = caddr[0];
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debug("Manufact ID: %02x\n", value);
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switch (value) {
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case 0x01: /*AMD_MANUFACT*/
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info->flash_id = FLASH_MAN_AMD;
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break;
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case 0x04: /*FUJ_MANUFACT*/
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info->flash_id = FLASH_MAN_FUJ;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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break;
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}
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value = caddr[1]; /* device ID */
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debug("Device ID: %02x\n", value);
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switch (value) {
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case AMD_ID_LV040B:
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info->flash_id += FLASH_AM040;
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info->sector_count = 8;
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info->size = 0x00080000;
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break; /* => 512Kb */
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default:
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info->flash_id = FLASH_UNKNOWN;
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return 0; /* => no or unknown flash */
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}
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flash_get_offsets((ulong)addr, &flash_info[0]);
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/*
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* read sector protection at sector address,
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* (A7 .. A0) = 0x02
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* D0 = 1 if protected
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*/
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caddr = (volatile unsigned char *)(info->start[i]);
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info->protect[i] = caddr[2] & 1;
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}
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/*
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* Prevent writes to uninitialized FLASH.
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*/
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if (info->flash_id != FLASH_UNKNOWN) {
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caddr = (volatile unsigned char *)info->start[0];
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*caddr = 0xF0; /* reset bank */
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}
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return info->size;
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}
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int flash_erase(flash_info_t *info, int s_first, int s_last)
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{
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volatile unsigned char *addr =
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(volatile unsigned char *)(info->start[0]);
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN)
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printf("- missing\n");
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else
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printf("- no sectors to erase\n");
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return 1;
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}
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if ((info->flash_id == FLASH_UNKNOWN) ||
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(info->flash_id > FLASH_AMD_COMP)) {
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printf("Can't erase unknown flash type - aborted\n");
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect])
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prot++;
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}
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if (prot) {
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printf("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf("\n");
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}
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l_sect = -1;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr[0x0555] = 0xAA;
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addr[0x02AA] = 0x55;
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addr[0x0555] = 0x80;
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addr[0x0555] = 0xAA;
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addr[0x02AA] = 0x55;
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (volatile unsigned char *)(info->start[sect]);
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addr[0] = 0x30;
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l_sect = sect;
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* wait at least 80us - let's wait 1 ms */
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udelay(1000);
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/*
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* We wait for the last triggered sector
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*/
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if (l_sect < 0)
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goto DONE;
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start = get_timer(0);
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last = start;
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addr = (volatile unsigned char *)(info->start[l_sect]);
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while ((addr[0] & 0xFF) != 0xFF) {
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now = get_timer(start);
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if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf("Timeout\n");
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return 1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc('.');
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last = now;
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}
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}
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DONE:
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/* reset to read mode */
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addr = (volatile unsigned char *)info->start[0];
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addr[0] = 0xF0; /* reset bank */
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printf(" done\n");
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return 0;
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}
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/*
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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l = addr - wp;
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if (l != 0) {
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data = 0;
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for (i = 0, cp = wp; i < l; ++i, ++cp)
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data = (data << 8) | (*(uchar *)cp);
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for (; i < 4 && cnt > 0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt == 0 && i < 4; ++i, ++cp)
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data = (data << 8) | (*(uchar *)cp);
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rc = write_word(info, wp, data);
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if (rc != 0)
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return rc;
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i = 0; i < 4; ++i)
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data = (data << 8) | *src++;
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rc = write_word(info, wp, data);
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if (rc != 0)
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return rc;
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0)
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return 0;
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i < 4; ++i, ++cp)
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data = (data << 8) | (*(uchar *)cp);
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return write_word(info, wp, data);
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}
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/*
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* Write a word to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_word(flash_info_t *info, ulong dest, ulong data)
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{
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volatile unsigned char *cdest, *cdata;
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volatile unsigned char *addr =
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(volatile unsigned char *)(info->start[0]);
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ulong start;
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int flag, count = 4 ;
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cdest = (volatile unsigned char *)dest ;
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cdata = (volatile unsigned char *)&data ;
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/* Check if Flash is (sufficiently) erased */
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if ((*((vu_long *)dest)&data) != data)
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return 2;
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while (count--) {
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr[0x0555] = 0xAA;
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addr[0x02AA] = 0x55;
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addr[0x0555] = 0xA0;
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*cdest = *cdata;
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* data polling for D7 */
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start = get_timer(0);
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while ((*cdest ^ *cdata) & 0x80) {
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
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return 1;
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}
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cdata++ ;
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cdest++ ;
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}
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return 0;
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}
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@ -1,253 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Modified by Udi Finkelstein
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*
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* This file includes communication routines for SMC1 that can run even if
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* SMC2 have already been initialized.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <commproc.h>
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#include <stdio_dev.h>
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#include <lcd.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SMC_INDEX 0
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#define PROFF_SMC PROFF_SMC1
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
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#define RBC823_KBD_BAUDRATE 38400
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#define CPM_KEYBOARD_BASE 0x1000
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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void smc1_setbrg (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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/* Set up the baud rate generator.
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* See 8xx_io/commproc.c for details.
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*
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* Wire BRG2 to SMC1, BRG1 to SMC2
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*/
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cp->cp_simode = 0x00001000;
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cp->cp_brgc2 =
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(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
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}
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int smc1_init (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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uint dpaddr;
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/* initialize pointers to SMC */
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sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
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up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
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/* Disable transmitter/receiver.
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*/
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 1;
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/* clear error conditions */
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#ifdef CONFIG_SYS_SDSR
|
||||
im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
|
||||
#else
|
||||
im->im_sdma.sdma_sdsr = 0x83;
|
||||
#endif
|
||||
|
||||
/* clear SDMA interrupt mask */
|
||||
#ifdef CONFIG_SYS_SDMR
|
||||
im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
|
||||
#else
|
||||
im->im_sdma.sdma_sdmr = 0x00;
|
||||
#endif
|
||||
|
||||
/* Use Port B for SMC1 instead of other functions.
|
||||
*/
|
||||
cp->cp_pbpar |= 0x000000c0;
|
||||
cp->cp_pbdir &= ~0x000000c0;
|
||||
cp->cp_pbodr &= ~0x000000c0;
|
||||
|
||||
/* Set the physical address of the host memory buffers in
|
||||
* the buffer descriptors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_ALLOC_DPRAM
|
||||
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
|
||||
#else
|
||||
dpaddr = CPM_KEYBOARD_BASE ;
|
||||
#endif
|
||||
|
||||
/* Allocate space for two buffer descriptors in the DP ram.
|
||||
* For now, this address seems OK, but it may have to
|
||||
* change with newer versions of the firmware.
|
||||
* damm: allocating space after the two buffers for rx/tx data
|
||||
*/
|
||||
|
||||
rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
|
||||
rbdf->cbd_bufaddr = (uint) (rbdf+2);
|
||||
rbdf->cbd_sc = 0;
|
||||
tbdf = rbdf + 1;
|
||||
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
|
||||
tbdf->cbd_sc = 0;
|
||||
|
||||
/* Set up the uart parameters in the parameter ram.
|
||||
*/
|
||||
up->smc_rbase = dpaddr;
|
||||
up->smc_tbase = dpaddr+sizeof(cbd_t);
|
||||
up->smc_rfcr = SMC_EB;
|
||||
up->smc_tfcr = SMC_EB;
|
||||
|
||||
/* Set UART mode, 8 bit, no parity, one stop.
|
||||
* Enable receive and transmit.
|
||||
*/
|
||||
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
|
||||
|
||||
/* Mask all interrupts and remove anything pending.
|
||||
*/
|
||||
sp->smc_smcm = 0;
|
||||
sp->smc_smce = 0xff;
|
||||
|
||||
/* Set up the baud rate generator.
|
||||
*/
|
||||
smc1_setbrg ();
|
||||
|
||||
/* Make the first buffer the only buffer.
|
||||
*/
|
||||
tbdf->cbd_sc |= BD_SC_WRAP;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
|
||||
|
||||
/* Single character receive.
|
||||
*/
|
||||
up->smc_mrblr = 1;
|
||||
up->smc_maxidl = 0;
|
||||
|
||||
/* Initialize Tx/Rx parameters.
|
||||
*/
|
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
|
||||
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
|
||||
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||||
;
|
||||
|
||||
/* Enable transmitter/receiver.
|
||||
*/
|
||||
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void smc1_putc(const char c)
|
||||
{
|
||||
volatile cbd_t *tbdf;
|
||||
volatile char *buf;
|
||||
volatile smc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
|
||||
|
||||
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
|
||||
|
||||
/* Wait for last character to go.
|
||||
*/
|
||||
|
||||
buf = (char *)tbdf->cbd_bufaddr;
|
||||
|
||||
*buf = c;
|
||||
tbdf->cbd_datlen = 1;
|
||||
tbdf->cbd_sc |= BD_SC_READY;
|
||||
__asm__("eieio");
|
||||
|
||||
while (tbdf->cbd_sc & BD_SC_READY) {
|
||||
WATCHDOG_RESET ();
|
||||
__asm__("eieio");
|
||||
}
|
||||
}
|
||||
|
||||
int smc1_getc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile unsigned char *buf;
|
||||
volatile smc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
unsigned char c;
|
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
|
||||
|
||||
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
|
||||
|
||||
/* Wait for character to show up.
|
||||
*/
|
||||
buf = (unsigned char *)rbdf->cbd_bufaddr;
|
||||
|
||||
while (rbdf->cbd_sc & BD_SC_EMPTY)
|
||||
WATCHDOG_RESET ();
|
||||
|
||||
c = *buf;
|
||||
rbdf->cbd_sc |= BD_SC_EMPTY;
|
||||
|
||||
return(c);
|
||||
}
|
||||
|
||||
int smc1_tstc(void)
|
||||
{
|
||||
volatile cbd_t *rbdf;
|
||||
volatile smc_uart_t *up;
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cpmp = &(im->im_cpm);
|
||||
|
||||
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
|
||||
|
||||
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
|
||||
|
||||
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
|
||||
}
|
||||
|
||||
/* search for keyboard and register it if found */
|
||||
int drv_keyboard_init(void)
|
||||
{
|
||||
int error = 0;
|
||||
struct stdio_dev kbd_dev;
|
||||
|
||||
if (0) {
|
||||
/* register the keyboard */
|
||||
memset (&kbd_dev, 0, sizeof(struct stdio_dev));
|
||||
strcpy(kbd_dev.name, "kbd");
|
||||
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
|
||||
kbd_dev.putc = NULL;
|
||||
kbd_dev.puts = NULL;
|
||||
kbd_dev.getc = smc1_getc;
|
||||
kbd_dev.tstc = smc1_tstc;
|
||||
error = stdio_register (&kbd_dev);
|
||||
} else {
|
||||
lcd_is_enabled = 0;
|
||||
lcd_disable();
|
||||
}
|
||||
return error;
|
||||
}
|
||||
|
|
@ -1,256 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "mpc8xx.h"
|
||||
#include <linux/mtd/doc2000.h>
|
||||
|
||||
extern int kbd_init(void);
|
||||
extern int drv_kbd_init(void);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (long int, long int *, long int);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF
|
||||
|
||||
const uint sdram_table[] =
|
||||
{
|
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM)
|
||||
*/
|
||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
|
||||
0x1FF77C47, /* last */
|
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM)
|
||||
*
|
||||
* This is no UPM entry point. The following definition uses
|
||||
* the remaining space to establish an initialization
|
||||
* sequence, which is executed by a RUN command.
|
||||
*
|
||||
*/
|
||||
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM)
|
||||
*/
|
||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
|
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM)
|
||||
*/
|
||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM)
|
||||
*/
|
||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
|
||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
|
||||
_NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM)
|
||||
*/
|
||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
|
||||
0xFFFFFC84, 0xFFFFFC07, /* last */
|
||||
_NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM)
|
||||
*/
|
||||
0x1FF7FC07, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
};
|
||||
|
||||
const uint static_table[] =
|
||||
{
|
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM)
|
||||
*/
|
||||
0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
|
||||
0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
|
||||
0xFFFFFC04, 0xFFFFFC05, /* last */
|
||||
_NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM)
|
||||
*/
|
||||
0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
|
||||
0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*
|
||||
* Test TQ ID string (TQM8xx...)
|
||||
* If present, check for "L" type (no second DRAM bank),
|
||||
* otherwise "L" type is assumed as default.
|
||||
*
|
||||
* Return 1 for "L" type, 0 else.
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
if (i < 0 || strncmp(buf, "TQM8", 4)) {
|
||||
printf ("### No HW ID - assuming RBC823\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
puts(buf);
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
long int size_b0, size8, size9;
|
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table,
|
||||
sizeof (sdram_table) / sizeof (uint));
|
||||
|
||||
/*
|
||||
* 1 Bank of 64Mbit x 2 devices
|
||||
*/
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
|
||||
memctl->memc_mar = 0x00000088;
|
||||
|
||||
/*
|
||||
* Map controller SDRAM bank 0
|
||||
*/
|
||||
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
|
||||
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
|
||||
udelay (200);
|
||||
|
||||
/*
|
||||
* Perform SDRAM initializsation sequence
|
||||
*/
|
||||
memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
|
||||
udelay (1);
|
||||
memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
|
||||
udelay (200);
|
||||
memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
|
||||
udelay (1);
|
||||
memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
|
||||
udelay (200);
|
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of
|
||||
* banks): This value is selected for four cycles every 62.4 us
|
||||
* with two SDRAM banks or four cycles every 31.2 us with one
|
||||
* bank. It will be adjusted after memory sizing.
|
||||
*/
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
|
||||
|
||||
/*
|
||||
* Check Bank 0 Memory Size for re-configuration
|
||||
*
|
||||
* try 8 column mode
|
||||
*/
|
||||
size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* try 9 column mode
|
||||
*/
|
||||
size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
|
||||
if (size8 < size9) { /* leave configuration at 9 columns */
|
||||
size_b0 = size9;
|
||||
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
|
||||
} else { /* back to 8 columns */
|
||||
size_b0 = size8;
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
|
||||
udelay (500);
|
||||
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
|
||||
}
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Adjust refresh rate depending on SDRAM type, both banks
|
||||
* For types > 128 MBit leave it at the current (fast) rate
|
||||
*/
|
||||
if ((size_b0 < 0x02000000)) {
|
||||
/* reduce to 15.6 us (62.4 us / quad) */
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
/* SDRAM Bank 0 is bigger - map first */
|
||||
|
||||
memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
|
||||
memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||
|
||||
udelay (10000);
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
|
||||
static long int dram_size (long int mamr_value, long int *base,
|
||||
long int maxsize)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size (base, maxsize));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_DOC
|
||||
void doc_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
upmconfig (UPMB, (uint *) static_table,
|
||||
sizeof (static_table) / sizeof (uint));
|
||||
memctl->memc_mbmr = MAMR_DSA_1_CYCL;
|
||||
|
||||
doc_probe (FLASH_BASE1_PRELIM);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
lib/built-in.o (.text*)
|
||||
net/built-in.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
|
||||
arch/powerpc/lib/built-in.o (.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1008,7 +1008,6 @@ Active powerpc mpc8xx - - netta2
|
|||
Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
|
||||
Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
|
||||
Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
|
||||
Active powerpc mpc8xx - - rbc823 RBC823 - -
|
||||
Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
|
||||
Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
|
||||
Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
rbc823 powerpc mpc8xx - -
|
||||
quantum powerpc mpc8xx - -
|
||||
RPXlite_dw powerpc mpc8xx - -
|
||||
qs850 powerpc mpc8xx - -
|
||||
|
|
|
|||
|
|
@ -292,9 +292,6 @@ void lcd_ctrl_init (void *lcdbase)
|
|||
|
||||
/* Initialize LCD controller bus priorities.
|
||||
*/
|
||||
#ifdef CONFIG_RBC823
|
||||
immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */
|
||||
#else
|
||||
immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
|
||||
|
||||
/* set SHFT/CLOCK division factor 4
|
||||
|
|
@ -308,21 +305,7 @@ void lcd_ctrl_init (void *lcdbase)
|
|||
immr->im_clkrst.car_sccr &= ~0x1F;
|
||||
immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
|
||||
|
||||
#endif /* CONFIG_RBC823 */
|
||||
|
||||
#if defined(CONFIG_RBC823)
|
||||
/* Enable LCD on port D.
|
||||
*/
|
||||
immr->im_ioport.iop_pddat &= 0x0300;
|
||||
immr->im_ioport.iop_pdpar |= 0x1CFF;
|
||||
immr->im_ioport.iop_pddir |= 0x1CFF;
|
||||
|
||||
/* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
|
||||
*/
|
||||
immr->im_cpm.cp_pbdat &= ~0x00005001;
|
||||
immr->im_cpm.cp_pbpar &= ~0x00005001;
|
||||
immr->im_cpm.cp_pbdir |= 0x00005001;
|
||||
#elif !defined(CONFIG_EDT32F10)
|
||||
#if !defined(CONFIG_EDT32F10)
|
||||
/* Enable LCD on port D.
|
||||
*/
|
||||
immr->im_ioport.iop_pdpar |= 0x1FFF;
|
||||
|
|
@ -427,18 +410,13 @@ void lcd_enable (void)
|
|||
volatile lcd823_t *lcdp = &immr->im_lcd;
|
||||
|
||||
/* Enable the LCD panel */
|
||||
#ifndef CONFIG_RBC823
|
||||
immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
|
||||
#endif
|
||||
lcdp->lcd_lccr |= LCCR_PON;
|
||||
|
||||
#ifdef CONFIG_V37
|
||||
/* Turn on display backlight */
|
||||
immr->im_cpm.cp_pbpar |= 0x00008000;
|
||||
immr->im_cpm.cp_pbdir |= 0x00008000;
|
||||
#elif defined(CONFIG_RBC823)
|
||||
/* Turn on display backlight */
|
||||
immr->im_cpm.cp_pbdat |= 0x00004000;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LWMON)
|
||||
|
|
@ -476,14 +454,6 @@ void lcd_enable (void)
|
|||
r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
|
||||
}
|
||||
#endif /* CONFIG_R360MPI */
|
||||
#ifdef CONFIG_RBC823
|
||||
udelay(200000); /* wait 200ms */
|
||||
/* Turn VEE_ON first */
|
||||
immr->im_cpm.cp_pbdat |= 0x00000001;
|
||||
udelay(200000); /* wait 200ms */
|
||||
/* Now turn on LCD_ON */
|
||||
immr->im_cpm.cp_pbdat |= 0x00001000;
|
||||
#endif
|
||||
#ifdef CONFIG_RRVISION
|
||||
debug ("PC4->Output(1): enable LVDS\n");
|
||||
debug ("PC5->Output(0): disable PAL clock\n");
|
||||
|
|
@ -503,41 +473,6 @@ void lcd_enable (void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#if defined (CONFIG_RBC823)
|
||||
void lcd_disable (void)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile lcd823_t *lcdp = &immr->im_lcd;
|
||||
|
||||
#if defined(CONFIG_LWMON)
|
||||
{ uchar c = pic_read (0x60);
|
||||
c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
|
||||
pic_write (0x60, c);
|
||||
}
|
||||
#elif defined(CONFIG_R360MPI)
|
||||
{
|
||||
extern void r360_i2c_lcd_write (uchar data0, uchar data1);
|
||||
|
||||
r360_i2c_lcd_write(0x10, 0x00);
|
||||
r360_i2c_lcd_write(0x20, 0x00);
|
||||
r360_i2c_lcd_write(0x30, 0x00);
|
||||
r360_i2c_lcd_write(0x40, 0x00);
|
||||
}
|
||||
#endif /* CONFIG_LWMON */
|
||||
/* Disable the LCD panel */
|
||||
lcdp->lcd_lccr &= ~LCCR_PON;
|
||||
#ifdef CONFIG_RBC823
|
||||
/* Turn off display backlight, VEE and LCD_ON */
|
||||
immr->im_cpm.cp_pbdat &= ~0x00005001;
|
||||
#else
|
||||
immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
|
||||
#endif /* CONFIG_RBC823 */
|
||||
}
|
||||
#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
|
||||
|
||||
|
||||
/************************************************************************/
|
||||
|
||||
#endif /* CONFIG_LCD */
|
||||
|
|
|
|||
|
|
@ -968,7 +968,7 @@ typedef struct scc_enet {
|
|||
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
|
||||
|
||||
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
|
||||
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
|
||||
defined(CONFIG_R360MPI) || \
|
||||
defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
|
||||
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
|
||||
defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
|
||||
|
|
|
|||
|
|
@ -1,407 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Modified by Udi Finkelstein udif@udif.com
|
||||
* For the RBC823 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
|
||||
#define CONFIG_RBC823 1 /* ...on a RBC823 module */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#if 0
|
||||
#define DEBUG 1
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
#endif
|
||||
#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
|
||||
#define CONFIG_LCD 1 /* use LCD controller ... */
|
||||
#define CONFIG_MPC8XX_LCD
|
||||
#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
|
||||
#undef CONFIG_8xx_CONS_SMC1
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||
#if 1
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
#define CONFIG_8xx_GCLK_FREQ 48000000L
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
#undef CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
|
||||
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 40000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_WRITE_BITS 4
|
||||
#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_BEDBUG
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_CDP
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_KGDB
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_PORTIO
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SAVES
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFF00000
|
||||
#if defined(DEBUG)
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
/*
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
*/
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* for 48 MHz, we use a 4 MHz clock * 12
|
||||
*/
|
||||
#define CONFIG_SYS_PLPRCR \
|
||||
( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
|
||||
SCCR_PRQEN | SCCR_EBDF00 | \
|
||||
SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
#ifdef NOT_USED
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/*#define CONFIG_SYS_DER 0x2002000F*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
|
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
|
||||
BR_PS_8 | BR_V)
|
||||
|
||||
/*
|
||||
* BR4 and OR4 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
/*
|
||||
* SDRAM timing:
|
||||
*/
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
|
||||
|
||||
#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
|
||||
#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT ""
|
||||
#define MTDPARTS_DEFAULT ""
|
||||
*/
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -258,10 +258,6 @@ extern vidinfo_t panel_info;
|
|||
|
||||
/* Video functions */
|
||||
|
||||
#if defined(CONFIG_RBC823)
|
||||
void lcd_disable(void);
|
||||
#endif
|
||||
|
||||
void lcd_putc(const char c);
|
||||
void lcd_puts(const char *s);
|
||||
void lcd_printf(const char *fmt, ...);
|
||||
|
|
|
|||
|
|
@ -231,25 +231,6 @@ void status_led_set (int led, int state);
|
|||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/***** RBC823 ********************************************************/
|
||||
#elif defined(CONFIG_RBC823)
|
||||
|
||||
# define STATUS_LED_PAR im_ioport.iop_pcpar
|
||||
# define STATUS_LED_DIR im_ioport.iop_pcdir
|
||||
# undef STATUS_LED_ODR
|
||||
# define STATUS_LED_DAT im_ioport.iop_pcdat
|
||||
|
||||
# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */
|
||||
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
# define STATUS_LED_STATE STATUS_LED_BLINKING
|
||||
# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */
|
||||
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
|
||||
# define STATUS_LED_STATE1 STATUS_LED_OFF
|
||||
|
||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
||||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/***** NetPhone ********************************************************/
|
||||
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
|
||||
/* XXX empty just to avoid the error */
|
||||
|
|
|
|||
Loading…
Reference in New Issue