SPI: mxc_spi: add support for i.MX35 processor
Signed-off-by: Stefano Babic <sbabic@denx.de>
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01bb24b642
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@ -70,6 +70,8 @@ static unsigned long spi_bases[] = {
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0x53f84000,
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};
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#define mxc_get_clock(x) mx31_get_ipg_clk()
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#elif defined(CONFIG_MX51)
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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@ -111,6 +113,45 @@ static unsigned long spi_bases[] = {
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CSPI2_BASE_ADDR,
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CSPI3_BASE_ADDR,
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};
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#elif defined(CONFIG_MX35)
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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};
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#else
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#error "Unsupported architecture"
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#endif
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@ -158,8 +199,35 @@ void spi_cs_deactivate(struct spi_slave *slave)
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!(mxcs->ss_pol));
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}
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#ifdef CONFIG_MX51
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static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
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#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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unsigned int ctrl_reg;
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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MXC_CSPICTRL_EN |
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#ifdef CONFIG_MX35
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MXC_CSPICTRL_SSCTL |
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#endif
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (mode & SPI_CPOL)
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->ctrl_reg = ctrl_reg;
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return 0;
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}
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#endif
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#if defined(CONFIG_MX51)
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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@ -227,7 +295,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
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/*
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* Configuration register setup
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* The MX51 has support different setup for each SS
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* The MX51 supports different setup for each SS
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*/
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
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(ss_pol << (cs + MXC_CSPICON_SSPOL));
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@ -363,7 +431,6 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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@ -441,7 +508,6 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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unsigned int ctrl_reg;
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struct mxc_spi_slave *mxcs;
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int ret;
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@ -467,30 +533,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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mxcs->base = spi_bases[bus];
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mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
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#ifdef CONFIG_MX51
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/* Can be used for i.MX31 too ? */
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ctrl_reg = 0;
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ret = spi_cfg(mxcs, cs, max_hz, mode);
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ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
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if (ret) {
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printf("mxc_spi: cannot setup SPI controller\n");
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free(mxcs);
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return NULL;
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}
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#else
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(31) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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MXC_CSPICTRL_EN |
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (mode & SPI_CPOL)
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->ctrl_reg = ctrl_reg;
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#endif
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return &mxcs->slave;
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}
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