From 432a6241bdb70b98ead8f58bbf717d3f7fe699a8 Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Mon, 19 Oct 2015 19:40:14 +0300 Subject: [PATCH 01/15] arm: add support for semihosting for ARMv7M targets If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html Signed-off-by: Vadzim Dambrouski --- arch/arm/lib/semihosting.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964eabc..ed5e8e426e 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); From 7bdf75ca5cf253276e3cfcf5af8da9029e50790f Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Mon, 19 Oct 2015 19:40:15 +0300 Subject: [PATCH 02/15] arm: fix compile warnings when semihosting is enabled on ARMv7M target. This patch fixes compile warnings like this: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' In C99 standard you can use %zu modifier to print size_t values. Signed-off-by: Vadzim Dambrouski --- arch/arm/lib/semihosting.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index ed5e8e426e..e32ad90945 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -92,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len) size_t len; } read; - debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len); + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); read.fd = fd; read.memp = memp; @@ -106,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len) * hard to maintain partial read loops and such, just fail * with an error message. */ - printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n", + printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n", __func__, ret, fd, len, memp); return -1; } From bf104ffa2594e5bf14ef2d5ac2711084c763ef77 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:39 +0200 Subject: [PATCH 03/15] stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD This target is ARMv7-M therefore can only build for Thumb, but it did not #define CONFIG_SYS_THUMB_BUILD, so the U-Boot code did not know it had to build for Thumb(2), not ARM. This patch is binary-invariant: builds of stm32f429-discovery with and without this patch were compared and found to differ only by their U-Boot version strings. Signed-off-by: Albert ARIBAUD --- include/configs/stm32f429-discovery.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 17969952d1..8191fb2b8a 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -9,6 +9,7 @@ #define __CONFIG_H #define CONFIG_STM32F4 +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_STM32F4DISCOVERY #define CONFIG_OF_LIBFDT From 62e92077a8936e60087d55683538ee386cc673aa Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:40 +0200 Subject: [PATCH 04/15] arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD --- Makefile | 2 + arch/arm/Kconfig | 5 ++ arch/arm/cpu/arm926ejs/Makefile | 11 +++ arch/arm/cpu/arm926ejs/cache.c | 5 ++ arch/arm/include/asm/cache.h | 4 ++ arch/arm/lib/Makefile | 24 +++++++ arch/arm/lib/cache.c | 11 +++ arch/arm/lib/memcpy.S | 4 +- arch/arm/lib/memset.S | 2 +- arch/arm/mach-orion5x/Makefile | 10 +++ .../arm/thumb1/include/asm/proc-armv/system.h | 69 +++++++++++++++++++ examples/standalone/Makefile | 10 +++ 12 files changed, 154 insertions(+), 3 deletions(-) create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h diff --git a/Makefile b/Makefile index 3c21f8ddf9..0bd8be2f78 100644 --- a/Makefile +++ b/Makefile @@ -605,6 +605,8 @@ KBUILD_CFLAGS += $(KCFLAGS) UBOOTINCLUDE := \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ + $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \ + -I$(srctree)/arch/$(ARCH)/thumb1/include),) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d756cbc55..5ab0254f3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -10,6 +10,9 @@ config ARM64 config HAS_VBAR bool +config HAS_THUMB2 + bool + config CPU_ARM720T bool @@ -32,9 +35,11 @@ config CPU_ARM1176 config CPU_V7 bool select HAS_VBAR + select HAS_THUMB2 config CPU_V7M bool + select HAS_THUMB2 config CPU_PXA bool diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 63fa159db6..fe78922170 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm + +endif +endif diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index e5c1a6ae6c..2839c863e8 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,4 +82,9 @@ void flush_dcache_all(void) /* * Stub implementations for l2 cache operations */ + __weak void l2_cache_disable(void) {} + +#if defined CONFIG_SYS_THUMB_BUILD +__weak void invalidate_l2_cache(void) {} +#endif diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index a836e9f2ab..1f63127bdc 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -16,6 +16,9 @@ /* * Invalidate L2 Cache using co-proc instruction */ +#ifdef CONFIG_SYS_THUMB_BUILD +void invalidate_l2_cache(void); +#else static inline void invalidate_l2_cache(void) { unsigned int val=0; @@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void) : : "r" (val) : "cc"); isb(); } +#endif void l2_cache_enable(void); void l2_cache_disable(void); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 2bdfaba5b7..f3db7b58cb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL) += debug.o ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +# for C files, just apend -marm, which will override previous -mthumb* + +CFLAGS_cache.o := -marm +CFLAGS_cache-cp15.o := -marm + +# For .S, drop -mthumb* and other thumb-related options. +# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_* +# was implemented and is used here. +# Also, define ${target}_NO_THUMB_BUILD for these two targets +# so that the code knows it should not use Thumb. + +AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork +AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork +AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD +AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD + +endif +endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index cd13db3440..3bd87105c5 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align) return next; } #endif /* CONFIG_SYS_NONCACHED_MEMORY */ + +#if defined(CONFIG_SYS_THUMB_BUILD) +void invalidate_l2_cache(void) +{ + unsigned int val = 0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} +#endif diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index eeaf003529..7d9fc0f9be 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -13,7 +13,7 @@ #include #include -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) #define W(instr) instr.w #else #define W(instr) instr @@ -62,7 +62,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 7208f20dda..df053a31d5 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -16,7 +16,7 @@ .align 5 .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 546ebcb52e..33dcad40f2 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -16,3 +16,13 @@ obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm + +endif +endif diff --git a/arch/arm/thumb1/include/asm/proc-armv/system.h b/arch/arm/thumb1/include/asm/proc-armv/system.h new file mode 100644 index 0000000000..7dfbf3d33d --- /dev/null +++ b/arch/arm/thumb1/include/asm/proc-armv/system.h @@ -0,0 +1,69 @@ +/* + * Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h + * + * (C) Copyright 2015 + * Albert ARIBAUD + * + * The original file does not build in Thumb mode. However, in U-Boot + * we don't use interrupt context, so we can redefine these as empty + * memory barriers, which makes Thumb-1 compiler happy. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Use the same macro name as linux/include/asm-arm/proc-armv/system.h + * here, so that if the original ever gets included after us, it won't + * try to re-redefine anything. + */ + +#ifndef __ASM_PROC_SYSTEM_H +#define __ASM_PROC_SYSTEM_H + +/* + * Redefine all original macros with static inline functions containing + * a simple memory barrier, so that they produce the same instruction + * ordering constraints as their original counterparts. + * We use static inline functions rather than macros so that we can tell + * the compiler to not complain about unused arguments. + */ + +static inline void local_irq_save( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_enable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_disable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __stf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __clf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_save_flags( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_restore( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +#endif /* __ASM_PROC_SYSTEM_H */ diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 0863a8cda2..5a6ae0013c 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -73,3 +73,13 @@ $(obj)/%.srec: $(obj)/% FORCE $(obj)/%.bin: OBJCOPYFLAGS := -O binary $(obj)/%.bin: $(obj)/% FORCE $(call if_changed,objcopy) + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_stubs.o := -marm + +endif +endif From 44b0e47ac0ee4c725ef3581608ac10c3648ba415 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:41 +0200 Subject: [PATCH 05/15] tricorder: switch to CONFIG_SYS_THUMB_BUILD The tricorder and tricorder_flash boards have grown too big. Reduce their size by building them with CONFIG_SYS_THUMB_BUILD. Signed-off-by: Albert ARIBAUD --- include/configs/tricorder.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 02b0e6351f..0ab69e665a 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -17,6 +17,7 @@ #define __CONFIG_H /* High Level Configuration Options */ +#define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON /* Common ARM Erratas */ From e7de61b3e4a7335cd50f52b820d710f8bd50d684 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:42 +0200 Subject: [PATCH 06/15] kirkwood: support CONFIG_SYS_THUMB_BUILD Kirkwood files cpu.c and cache.c cannot build in Thumb state; force them in ARM state even under CONFIG_SYS_THUMB_BUILD. Signed-off-by: Albert ARIBAUD --- arch/arm/mach-kirkwood/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index df4756e4bd..5abcf70b28 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -9,3 +9,9 @@ obj-y = cpu.o obj-y += cache.o obj-y += mpp.o + +# cpu.o and cache.o contain CP15 instructions which cannot be run in +# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm From 35629363733a8e68c61f6698eaaeffdf66d3ec65 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:43 +0200 Subject: [PATCH 07/15] Revive OpenRD targets Revert commit 7a2c1b13 which dropped OpenRD boards. Assume maintainership of OpenRD. Remove OpenRD from scrapyard. Switch OpenRD to generic board. Switch to Thumb build. Signed-off-by: Albert ARIBAUD --- arch/arm/mach-kirkwood/Kconfig | 4 + board/Marvell/openrd/Kconfig | 12 +++ board/Marvell/openrd/MAINTAINERS | 12 +++ board/Marvell/openrd/Makefile | 14 +++ board/Marvell/openrd/kwbimage.cfg | 152 ++++++++++++++++++++++++++++ board/Marvell/openrd/openrd.c | 160 ++++++++++++++++++++++++++++++ board/Marvell/openrd/openrd.h | 30 ++++++ configs/openrd_base_defconfig | 7 ++ configs/openrd_client_defconfig | 7 ++ configs/openrd_ultimate_defconfig | 7 ++ doc/README.scrapyard | 3 - include/configs/openrd.h | 138 ++++++++++++++++++++++++++ 12 files changed, 543 insertions(+), 3 deletions(-) create mode 100644 board/Marvell/openrd/Kconfig create mode 100644 board/Marvell/openrd/MAINTAINERS create mode 100644 board/Marvell/openrd/Makefile create mode 100644 board/Marvell/openrd/kwbimage.cfg create mode 100644 board/Marvell/openrd/openrd.c create mode 100644 board/Marvell/openrd/openrd.h create mode 100644 configs/openrd_base_defconfig create mode 100644 configs/openrd_client_defconfig create mode 100644 configs/openrd_ultimate_defconfig create mode 100644 include/configs/openrd.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index aab5d19b5f..f7737bfb22 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,6 +4,9 @@ choice prompt "Marvell Kirkwood board select" optional +config TARGET_OPENRD + bool "Marvell OpenRD Board" + config TARGET_DREAMPLUG bool "DreamPlug Board" @@ -51,6 +54,7 @@ endchoice config SYS_SOC default "kirkwood" +source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig new file mode 100644 index 0000000000..124b66da0f --- /dev/null +++ b/board/Marvell/openrd/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OPENRD + +config SYS_BOARD + default "openrd" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "openrd" + +endif diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS new file mode 100644 index 0000000000..3789a04c89 --- /dev/null +++ b/board/Marvell/openrd/MAINTAINERS @@ -0,0 +1,12 @@ +OPENRD BOARD +M: Albert ARIBAUD +S: Maintained +F: board/Marvell/openrd/ +F: include/configs/openrd.h +F: configs/openrd_base_defconfig + +OPENRD_CLIENT BOARD +M: Albert ARIBAUD +S: Maintained +F: configs/openrd_client_defconfig +F: configs/openrd_ultimate_defconfig diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile new file mode 100644 index 0000000000..8f95b7922e --- /dev/null +++ b/board/Marvell/openrd/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2009 +# Net Insight +# Written-by: Simon Kagstrom +# +# Based on sheevaplug: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := openrd.o diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg new file mode 100644 index 0000000000..8e5993715e --- /dev/null +++ b/board/Marvell/openrd/kwbimage.cfg @@ -0,0 +1,152 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strength reduced +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) + +DATA 0xFFD0149C 0x0000E40f # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c new file mode 100644 index 0000000000..17a65600e4 --- /dev/null +++ b/board/Marvell/openrd/openrd.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.c: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "openrd.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, /* Alt UART1_TXD */ + MPP14_SD_D0, /* Alt UART1_RXD */ + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* UART1 / SD sel */ + MPP35_TDM_CH0_TX_QL, + MPP36_TDM_SPI_CS1, + MPP37_TDM_CH2_TX_QL, + MPP38_TDM_CH2_RX_QL, + MPP39_AUDIO_I2SBCLK, + MPP40_AUDIO_I2SDO, + MPP41_AUDIO_I2SLRC, + MPP42_AUDIO_I2SMCLK, + MPP43_AUDIO_I2SDI, + MPP44_AUDIO_EXTCLK, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_TDM_CH0_RX_QL, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ +#if defined(CONFIG_BOARD_IS_OPENRD_BASE) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; +#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; +#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; +#endif + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116/88E1121 PHY */ +void mv_phy_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf(PHY_NO" Initialized on %s\n", name); +} + +void reset_phy(void) +{ + mv_phy_init("egiga0"); + +#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT + /* Kirkwood ethernet driver is written with the assumption that in case + * of multiple PHYs, their addresses are consecutive. But unfortunately + * in case of OpenRD-Client, PHY addresses are not consecutive.*/ + miiphy_write("egiga1", 0xEE, 0xEE, 24); +#endif + +#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ + defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) + /* configure and initialize both PHY's */ + mv_phy_init("egiga1"); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h new file mode 100644 index 0000000000..56dfeea1a8 --- /dev/null +++ b/board/Marvell/openrd/openrd.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OPENRD_BASE_H +#define __OPENRD_BASE_H + +#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ +#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ +#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __OPENRD_BASE_H */ diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig new file mode 100644 index 0000000000..16861397c3 --- /dev/null +++ b/configs/openrd_base_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig new file mode 100644 index 0000000000..c34231560c --- /dev/null +++ b/configs/openrd_client_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig new file mode 100644 index 0000000000..530ba4d10c --- /dev/null +++ b/configs/openrd_ultimate_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_OPENRD=y +CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 728acddb5a..b7cf62df9b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -64,9 +64,6 @@ nhk8815 arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linu nhk8815_onenand arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team omap3_mvblx arm armv7 8dc372f9 2015-08-30 Michael Jones omap3_sdp3430 arm armv7 93b25c08 2015-08-30 Nishanth Menon -openrd_base arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar -openrd_client arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar -openrd_ultimate arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar otc570 arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski otc570_dataflash arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski palmld arm pxa 35782e9c 2015-08-30 Marek Vasut diff --git a/include/configs/openrd.h b/include/configs/openrd.h new file mode 100644 index 0000000000..62f15b7688 --- /dev/null +++ b/include/configs/openrd.h @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2009 + * Net Insight + * Written-by: Simon Kagstrom + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * Version number information + */ +#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" +#else +# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT +# define CONFIG_IDENT_STRING "\nOpenRD-Client" +# else +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_IDENT_STRING "\nOpenRD-Base" +# else +# error Unknown OpenRD board specified +# endif +# endif +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_THUMB_BUILD + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +# ifdef CONFIG_BOARD_IS_OPENRD_BASE +# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +# else +# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +# endif +# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE +# define CONFIG_PHY_BASE_ADR 0x0 +# define PHY_NO "88E1121" +# else +# define CONFIG_PHY_BASE_ADR 0x8 +# define PHY_NO "88E1116" +# endif +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MVEBU_MMC +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE +#endif /* CONFIG_CMD_MMC */ + +#endif /* _CONFIG_OPENRD_BASE_H */ From 4cd3246f2a3a3a5032edcaed3cf807dd916f0aea Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Fri, 23 Oct 2015 21:14:06 +0300 Subject: [PATCH 08/15] arm: stm32f4: fix a bug when only first sector gets erased flash_lock call is inside a for loop, so after the first iteration flash is locked and no more sectors can be erased. Move flash_lock out of the loop. Signed-off-by: Vadzim Dambrouski --- arch/arm/cpu/armv7m/stm32f4/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index e5c6111330..ae6379070f 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -114,9 +114,9 @@ int flash_erase(flash_info_t *info, int first, int last) ; clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); - stm32f4_flash_lock(1); } + stm32f4_flash_lock(1); return 0; } From 43fb0e3926dc52d4618d172a388cb6750311193d Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Fri, 23 Oct 2015 21:14:07 +0300 Subject: [PATCH 09/15] arm: stm32f4: fix a bug when a random sector gets erased Old sector number is not being cleared from FLASH_CR register. For example when first erased sector was 001 and then you want to erase sector 010, sector 011 gets erased instead. This patch clears old sector number from FLASH_CR register before a new one is written. Signed-off-by: Vadzim Dambrouski --- arch/arm/cpu/armv7m/stm32f4/flash.c | 3 +++ arch/arm/include/asm/arch-stm32f4/stm32.h | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index ae6379070f..dd058bd643 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last) while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) ; + /* clear old sector number before writing a new one */ + clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); + if (bank == 0) { setbits_le32(&STM32_FLASH->cr, (i << STM32_FLASH_CR_SNB_OFFSET)); diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 3ed3801dfe..7ca6dc3de8 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -104,6 +104,7 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_STRT (1 << 16) #define STM32_FLASH_CR_LOCK (1 << 31) #define STM32_FLASH_CR_SNB_OFFSET 3 +#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) enum clock { CLOCK_CORE, From 3a90cb676fdb039c16de1d63cdd25cac7dbec322 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 10 Nov 2015 09:14:38 -0500 Subject: [PATCH 10/15] board/ti: Update MAINTAINERS entries with more boards A few config files have been added without updating MAINTAINERS. Reported-by: Albert ARIBAUD Signed-off-by: Tom Rini --- board/ti/am335x/MAINTAINERS | 1 + board/ti/am43xx/MAINTAINERS | 2 ++ board/ti/dra7xx/MAINTAINERS | 2 ++ 3 files changed, 5 insertions(+) diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS index c99e06dc10..7dc2b83839 100644 --- a/board/ti/am335x/MAINTAINERS +++ b/board/ti/am335x/MAINTAINERS @@ -6,6 +6,7 @@ F: include/configs/am335x_evm.h F: configs/am335x_boneblack_defconfig F: configs/am335x_boneblack_vboot_defconfig F: configs/am335x_evm_defconfig +F: configs/am335x_gp_evm_defconfig F: configs/am335x_evm_nor_defconfig F: configs/am335x_evm_norboot_defconfig F: configs/am335x_evm_spiboot_defconfig diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS index 3d40b171d2..96ef85b462 100644 --- a/board/ti/am43xx/MAINTAINERS +++ b/board/ti/am43xx/MAINTAINERS @@ -7,3 +7,5 @@ F: configs/am43xx_evm_defconfig F: configs/am43xx_evm_qspiboot_defconfig F: configs/am43xx_evm_ethboot_defconfig F: configs/am43xx_evm_usbhost_boot_defconfig +F: configs/am437x_gp_evm_defconfig +F: configs/am437x_sk_evm_defconfig diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS index 5ec67697cf..3f638d0a7e 100644 --- a/board/ti/dra7xx/MAINTAINERS +++ b/board/ti/dra7xx/MAINTAINERS @@ -3,6 +3,8 @@ M: Lokesh Vutla S: Maintained F: board/ti/dra7xx/ F: include/configs/dra7xx_evm.h +F: configs/dra72_evm_defconfig +F: configs/dra74_evm_defconfig F: configs/dra7xx_evm_defconfig F: configs/dra7xx_evm_qspiboot_defconfig F: configs/dra7xx_evm_uart3_defconfig From 9549867c861fdb186512df7593f543d5fe2020f4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Nov 2015 13:41:03 -0200 Subject: [PATCH 11/15] ls1043ardb: Add missing config entries to MAINTAINERS ls1043ardb_nand_defconfig and ls1043ardb_sdcard_defconfig are missing in the MAINTAINERS file, so add them for completeness. Reported-by: Albert Aribaud Signed-off-by: Fabio Estevam Reviewed-by: Albert ARIBAUD --- board/freescale/ls1043ardb/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index b8f6be249f..efca5bf245 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -5,3 +5,5 @@ F: board/freescale/ls1043ardb/ F: board/freescale/ls1043ardb/ls1043ardb.c F: include/configs/ls1043ardb.h F: configs/ls1043ardb_defconfig +F: configs/ls1043ardb_nand_defconfig +F: configs/ls1043ardb_sdcard_defconfig From 88f965d720b745431a1fbe9107c561b7f381026c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:08:59 -0600 Subject: [PATCH 12/15] armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren --- arch/arm/include/asm/system.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index cfc7834ed9..71b31085b4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -17,6 +17,7 @@ #define PGTABLE_SIZE (0x10000) /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 +#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) #ifndef __ASSEMBLY__ @@ -278,11 +279,6 @@ enum { */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -#ifdef CONFIG_SYS_NONCACHED_MEMORY -void noncached_init(void); -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) @@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align); void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init(void); +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + #endif /* __ASSEMBLY__ */ #endif From 3c6af3bad4f644e050f67146f4a6e177d5e39e76 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:09:00 -0600 Subject: [PATCH 13/15] armv8: allow custom MMU setup routines on ARMv8 In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren --- arch/arm/cpu/armv8/cache_v8.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index b1ea8227cb..1ece6a2c12 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +__weak void mmu_setup(void) { bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; From 376cb1a4531538a031f3875f0aab21f31f8f8c90 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:09:01 -0600 Subject: [PATCH 14/15] ARM: tegra: add custom MMU setup on ARMv8 This sets up a fine-grained page table, which is a requirement for noncached_init() to operate correctly. MMU setup code currently exists in a number of places: - A version in the core ARMv8 support code that sets up page tables that use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't support. - Enhanced versions for fsl-lsch3 and zynmq that set up finer grained page tables. Ideally, rather than duplicating the MMU setup code yet again this patch would instead consolidate all the different routines into the core ARMv8 code so that it supported all use-cases. However, this will require significant effort since there appear to be a number of discrepancies[1] between different versions of the code, and between the defines/values by some copies of the MMU setup code use and the architectural MMU documentation. Some reverse engineering will be required to determine the intent of the current code. [1] For example, in the core ARMv8 MMU setup code, three defines named TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and the others set a different field (T1SZ) in the page tables. As far as I can tell so far, there should be no need to set different values per exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't be enabled anyway. Another example is inconsistent values for *_VA_BITS between the current core ARMv8 MMU setup code and the various SoC- specific MMU setup code. Another example is that asm/armv8/mmu.h's value for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT; research is needed to determine which code relies on which of those values and why, and whether fixing the incorrect value will cause any regression. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/arm64-mmu.c | 131 ++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm/mach-tegra/arm64-mmu.c diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 75924ad848..98431a91f8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o obj-$(CONFIG_PWM_TEGRA) += pwm.o endif +obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c new file mode 100644 index 0000000000..c2276523cb --- /dev/null +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) + +#define TCR_TG1_4K (1 << 31) +#define TCR_EPD1_DISABLE (1 << 23) +#define TEGRA_VA_BITS 40 +#define TEGRA_TCR TCR_TG1_4K | \ + TCR_EPD1_DISABLE | \ + TCR_SHARED_OUTER | \ + TCR_SHARED_INNER | \ + TCR_IRGN_WBWA | \ + TCR_ORGN_WBWA | \ + TCR_T0SZ(TEGRA_VA_BITS) + +#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ + PMD_ATTRINDX(MT_NORMAL) | \ + PMD_TYPE_SECT +#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ + PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ + PMD_TYPE_SECT + +/* 4K size is required to place 512 entries in each level */ +#define TLB_TABLE_SIZE 0x1000 + +/* + * This mmu table looks as below + * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 + * and other Level1 Table1. + * Level1 Table0 contains entries for each 1GB from 0 to 511GB. + * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. + * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains + * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. + */ +void mmu_setup(void) +{ + int el; + u64 i, section_l1t0, section_l1t1; + u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); + u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); + u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0, covering 0 to 512GB + * set level 1 table 1, covering 512GB to 1TB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + + for (i = 0; i < 512; i++) { + level1_table_0[i] = section_l1t0; + if (i >= 4) + level1_table_0[i] |= MEMORY_ATTR; + level1_table_1[i] = section_l1t1; + level1_table_1[i] |= MEMORY_ATTR; + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + level1_table_0[2] = + (u64)level2_table_2 | PMD_TYPE_TABLE; + level1_table_0[3] = + (u64)level2_table_3 | PMD_TYPE_TABLE; + + section_l2t0 = 0; + section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ + section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ + section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ + + for (i = 0; i < 512; i++) { + level2_table_0[i] = section_l2t0 | DEVICE_ATTR; + level2_table_1[i] = section_l2t1 | DEVICE_ATTR; + level2_table_2[i] = section_l2t2 | MEMORY_ATTR; + level2_table_3[i] = section_l2t3 | MEMORY_ATTR; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; + section_l2t2 += BLOCK_SIZE_L2; + section_l2t3 += BLOCK_SIZE_L2; + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TEGRA_TCR, MEMORY_ATTRIBUTES); + + set_sctlr(get_sctlr() | CR_M); +} + +u64 *arch_get_page_table(void) +{ + return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); +} From 5e68ff3949a3eebf62ba639171814f39c8e46a84 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:09:02 -0600 Subject: [PATCH 15/15] ARM: tegra: enable CONFIG_SYS_NONCACHED_MEMORY everywhere Now that we have solved the problems that prevented this feature from being enabled, enable it everywhere. Signed-off-by: Stephen Warren --- include/configs/tegra-common-post.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 651c4c4935..68da23e8b7 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ #endif -#ifndef CONFIG_ARM64 #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ -#endif #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \