OMAP3: Print correct silicon revision
The function display_board_info() displays incorrect silicon revision - based on the return value from function get_cpu_rev(). This patch fixes the problem. Signed-off-by: Sanjeev Premi <premi@ti.com>
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@ -101,7 +101,7 @@ void l2cache_enable()
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() == CPU_3430_ES2) {
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if (get_cpu_rev() >= CPU_3XX_ES20) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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@ -131,7 +131,7 @@ void l2cache_disable()
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volatile unsigned int j;
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/* ES2 onwards we can disable/enable L2 ourselves */
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if (get_cpu_rev() == CPU_3430_ES2) {
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if (get_cpu_rev() >= CPU_3XX_ES20) {
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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@ -132,7 +132,7 @@ void prcm_init(void)
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void (*f_lock_pll) (u32, u32, u32, u32);
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int xip_safe, p0, p1, p2, p3;
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u32 osc_clk = 0, sys_clkin_sel;
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u32 clk_index, sil_index;
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u32 clk_index, sil_index = 0;
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prm_t *prm_base = (prm_t *)PRM_BASE;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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dpll_param *dpll_param_p;
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@ -170,7 +170,8 @@ void prcm_init(void)
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* and sil_index will get the values for that SysClk for the
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* appropriate silicon rev.
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*/
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sil_index = get_cpu_rev() - 1;
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if (get_cpu_rev())
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sil_index = 1;
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/* Unlock MPU DPLL (slows things down, and needed later) */
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sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
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@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo;
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static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
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static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
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static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
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static char *rev_s[CPU_3XX_MAX_REV] = {
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"1.0",
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"2.0",
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"2.1",
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"3.0",
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"3.1"};
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/*****************************************************************
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* dieid_num_r(void) - read and set die ID
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@ -76,18 +82,27 @@ u32 get_cpu_type(void)
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u32 get_cpu_rev(void)
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{
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u32 cpuid = 0;
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ctrl_id_t *id_base;
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/*
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* On ES1.0 the IDCODE register is not exposed on L4
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* so using CPU ID to differentiate
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* between ES2.0 and ES1.0.
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* so using CPU ID to differentiate between ES1.0 and > ES1.0.
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*/
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__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
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if ((cpuid & 0xf) == 0x0)
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return CPU_3430_ES1;
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else
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return CPU_3430_ES2;
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return CPU_3XX_ES10;
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else {
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/* Decode the IDs on > ES1.0 */
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id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
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cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
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/* Some early ES2.0 seem to report ID 0, fix this */
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if(cpuid == 0)
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cpuid = CPU_3XX_ES20;
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return cpuid;
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}
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}
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/****************************************************
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@ -277,8 +292,8 @@ int print_cpuinfo (void)
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sec_s = "?";
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}
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printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
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sec_s, get_cpu_rev());
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printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
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cpu_s, sec_s, rev_s[get_cpu_rev()]);
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return 0;
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}
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@ -167,12 +167,16 @@ typedef struct gpio {
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* 343x real hardware:
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* ES1 = rev 0
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*
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* 343x code defines:
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* ES1 = 0+1 = 1
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* ES1 = 1+1 = 1
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* ES2 onwards, the value maps to contents of IDCODE register [31:28].
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*/
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#define CPU_3430_ES1 1
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#define CPU_3430_ES2 2
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#define CPU_3XX_ES10 0
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#define CPU_3XX_ES20 1
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#define CPU_3XX_ES21 2
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#define CPU_3XX_ES30 3
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#define CPU_3XX_ES31 4
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#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
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#define CPU_3XX_ID_SHIFT 28
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#define WIDTH_8BIT 0x0000
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#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
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