ppc: Zap TQM8260 board
This board is old and is using CONFIG_I2C_X, which is wrong. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de>utp
Marek Vasut
Wolfgang Denk
parent
6afb3574c9
commit
ccc1950010
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@ -55,9 +55,6 @@ config TARGET_VOVPN_GW
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config TARGET_KM82XX
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bool "Support km82xx"
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config TARGET_TQM8260
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bool "Support TQM8260"
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config TARGET_TQM8272
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bool "Support TQM8272"
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@ -79,7 +76,6 @@ source "board/pm826/Kconfig"
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source "board/pm828/Kconfig"
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source "board/ppmc8260/Kconfig"
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source "board/sacsng/Kconfig"
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source "board/tqc/tqm8260/Kconfig"
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source "board/tqc/tqm8272/Kconfig"
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endmenu
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@ -1,12 +0,0 @@
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if TARGET_TQM8260
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config SYS_BOARD
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default "tqm8260"
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config SYS_VENDOR
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default "tqc"
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config SYS_CONFIG_NAME
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default "TQM8260"
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endif
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@ -1,16 +0,0 @@
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TQM8260 BOARD
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M: Wolfgang Denk <wd@denx.de>
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S: Maintained
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F: board/tqc/tqm8260/
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F: include/configs/TQM8260.h
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F: configs/TQM8255_AA_defconfig
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F: configs/TQM8260_AA_defconfig
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F: configs/TQM8260_AB_defconfig
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F: configs/TQM8260_AC_defconfig
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F: configs/TQM8260_AD_defconfig
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F: configs/TQM8260_AE_defconfig
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F: configs/TQM8260_AF_defconfig
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F: configs/TQM8260_AG_defconfig
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F: configs/TQM8260_AH_defconfig
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F: configs/TQM8260_AI_defconfig
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F: configs/TQM8265_AA_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
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@ -1,415 +0,0 @@
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This file contains basic information on the port of U-Boot to TQM8260.
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All the changes fit in the common U-Boot infrastructure, providing a
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new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260,
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type "make TQM8260_config", edit the "include/config_TQM8260.h" file
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if necessary, then type "make".
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Common file modifications:
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--------------------------
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The following common files have been modified by this project:
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(starting from the ppcboot-0.9.3/ directory)
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MAKEALL - TQM8260 entry added
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Makefile - TQM8260_config entry added
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arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added
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arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
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bug fixed (fcr -> scr)
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arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
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include/flash.h - added definitions for the AM29LV640D Flash chip
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New files:
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----------
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The following new files have been added by this project:
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(starting from the ppcboot-0.9.3/ directory)
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board/tqm8260/ - board-specific directory
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board/tqm8260/Makefile - board-specific makefile
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board/tqm8260/config.mk - config file
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board/tqm8260/flash.c - flash driver (for AM29LV640D)
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board/tqm8260/ppcboot.lds - linker script
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board/tqm8260/tqm8260.c - ioport and memory initialization
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arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
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include/config_TQM8260.h - main configuration file
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New configuration options:
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--------------------------
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CONFIG_TQM8260
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Main board-specific option (should be defined for TQM8260).
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CONFIG_82xx_CONS_SMC1
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If defined, SMC1 will be used as the console
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CONFIG_82xx_CONS_SMC2
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If defined, SMC2 will be used as the console
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CONFIG_SYS_INIT_LOCAL_SDRAM
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If defined, the SDRAM on the local bus will be initialized and
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mapped at BR2.
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Acceptance criteria tests:
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--------------------------
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The following tests have been conducted to validate the port of U-Boot
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to TQM8260:
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1. Operation on serial console:
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With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file,
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the U-Boot output appeared on the serial terminal connected to COM1 as
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follows:
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------------------------------------------------------------------------------
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=> help
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go - start application at address 'addr'
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run - run commands in an environment variable
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bootm - boot application image from memory
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bootp - boot image via network using BootP/TFTP protocol
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tftpboot- boot image via network using TFTP protocol
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and env variables ipaddr and serverip
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rarpboot- boot image via network using RARP/TFTP protocol
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bootd - boot default, i.e., run 'bootcmd'
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loads - load S-Record file over serial line
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loadb - load binary file over serial line (kermit mode)
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md - memory display
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mm - memory modify (auto-incrementing)
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nm - memory modify (constant address)
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mw - memory write (fill)
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cp - memory copy
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cmp - memory compare
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crc32 - checksum calculation
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base - print or set address offset
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printenv- print environment variables
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setenv - set environment variables
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saveenv - save environment variables to persistent storage
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protect - enable or disable FLASH write protection
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erase - erase FLASH memory
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flinfo - print FLASH memory information
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bdinfo - print Board Info structure
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iminfo - print header information for application image
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coninfo - print console devices and informations
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eeprom - EEPROM sub-system
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loop - infinite loop on address range
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mtest - simple RAM test
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icache - enable or disable instruction cache
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dcache - enable or disable data cache
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reset - Perform RESET of the CPU
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echo - echo args to console
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version - print monitor version
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help - print online help
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? - alias for 'help'
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=>
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------------------------------------------------------------------------------
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2. Flash driver operation
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The following sequence was performed to test the "flinfo" command:
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------------------------------------------------------------------------------
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=> flinfo
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Bank # 1: AMD 29LV640D (64 M, uniform sector)
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Size: 32 MB in 128 Sectors
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Sector Start Addresses:
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40000000 40040000 (RO) 40080000 400C0000 40100000
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40140000 40180000 401C0000 40200000 40240000
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40280000 402C0000 40300000 40340000 40380000
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403C0000 40400000 40440000 40480000 404C0000
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40500000 40540000 40580000 405C0000 40600000
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40640000 40680000 406C0000 40700000 40740000
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40780000 407C0000 40800000 40840000 40880000
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408C0000 40900000 40940000 40980000 409C0000
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40A00000 40A40000 40A80000 40AC0000 40B00000
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40B40000 40B80000 40BC0000 40C00000 40C40000
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40C80000 40CC0000 40D00000 40D40000 40D80000
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40DC0000 40E00000 40E40000 40E80000 40EC0000
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40F00000 40F40000 40F80000 40FC0000 41000000
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41040000 41080000 410C0000 41100000 41140000
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41180000 411C0000 41200000 41240000 41280000
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412C0000 41300000 41340000 41380000 413C0000
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41400000 41440000 41480000 414C0000 41500000
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41540000 41580000 415C0000 41600000 41640000
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41680000 416C0000 41700000 41740000 41780000
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417C0000 41800000 41840000 41880000 418C0000
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41900000 41940000 41980000 419C0000 41A00000
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41A40000 41A80000 41AC0000 41B00000 41B40000
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41B80000 41BC0000 41C00000 41C40000 41C80000
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41CC0000 41D00000 41D40000 41D80000 41DC0000
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41E00000 41E40000 41E80000 41EC0000 41F00000
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41F40000 41F80000 41FC0000
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=>
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------------------------------------------------------------------------------
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The following sequence was performed to test the erase command:
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------------------------------------------------------------------------------
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=> cp 0 40080000 10
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Copy to Flash... done
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=> erase 40080000 400bffff
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Erase Flash from 0x40080000 to 0x400bffff
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.. done
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Erased 1 sectors
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=> md 40080000
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40080000: ffffffff ffffffff ffffffff ffffffff ................
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40080010: ffffffff ffffffff ffffffff ffffffff ................
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40080020: ffffffff ffffffff ffffffff ffffffff ................
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40080030: ffffffff ffffffff ffffffff ffffffff ................
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40080040: ffffffff ffffffff ffffffff ffffffff ................
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40080050: ffffffff ffffffff ffffffff ffffffff ................
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40080060: ffffffff ffffffff ffffffff ffffffff ................
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40080070: ffffffff ffffffff ffffffff ffffffff ................
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40080080: ffffffff ffffffff ffffffff ffffffff ................
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40080090: ffffffff ffffffff ffffffff ffffffff ................
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400800a0: ffffffff ffffffff ffffffff ffffffff ................
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400800b0: ffffffff ffffffff ffffffff ffffffff ................
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400800c0: ffffffff ffffffff ffffffff ffffffff ................
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400800d0: ffffffff ffffffff ffffffff ffffffff ................
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400800e0: ffffffff ffffffff ffffffff ffffffff ................
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400800f0: ffffffff ffffffff ffffffff ffffffff ................
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=> cp 0 40080000 10
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Copy to Flash... done
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=> erase 1:2
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Erase Flash Sectors 2-2 in Bank # 1
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.. done
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=> md 40080000
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40080000: ffffffff ffffffff ffffffff ffffffff ................
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40080010: ffffffff ffffffff ffffffff ffffffff ................
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40080020: ffffffff ffffffff ffffffff ffffffff ................
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40080030: ffffffff ffffffff ffffffff ffffffff ................
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40080040: ffffffff ffffffff ffffffff ffffffff ................
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40080050: ffffffff ffffffff ffffffff ffffffff ................
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40080060: ffffffff ffffffff ffffffff ffffffff ................
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40080070: ffffffff ffffffff ffffffff ffffffff ................
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40080080: ffffffff ffffffff ffffffff ffffffff ................
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40080090: ffffffff ffffffff ffffffff ffffffff ................
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400800a0: ffffffff ffffffff ffffffff ffffffff ................
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400800b0: ffffffff ffffffff ffffffff ffffffff ................
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400800c0: ffffffff ffffffff ffffffff ffffffff ................
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400800d0: ffffffff ffffffff ffffffff ffffffff ................
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400800e0: ffffffff ffffffff ffffffff ffffffff ................
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400800f0: ffffffff ffffffff ffffffff ffffffff ................
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=> cp 0 40080000 10
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Copy to Flash... done
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=> cp 0 400c0000 10
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Copy to Flash... done
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=> erase 1:2-3
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Erase Flash Sectors 2-3 in Bank # 1
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... done
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=> md 40080000
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40080000: ffffffff ffffffff ffffffff ffffffff ................
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40080010: ffffffff ffffffff ffffffff ffffffff ................
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40080020: ffffffff ffffffff ffffffff ffffffff ................
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40080030: ffffffff ffffffff ffffffff ffffffff ................
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40080040: ffffffff ffffffff ffffffff ffffffff ................
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40080050: ffffffff ffffffff ffffffff ffffffff ................
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40080060: ffffffff ffffffff ffffffff ffffffff ................
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40080070: ffffffff ffffffff ffffffff ffffffff ................
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40080080: ffffffff ffffffff ffffffff ffffffff ................
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40080090: ffffffff ffffffff ffffffff ffffffff ................
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400800a0: ffffffff ffffffff ffffffff ffffffff ................
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400800b0: ffffffff ffffffff ffffffff ffffffff ................
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400800c0: ffffffff ffffffff ffffffff ffffffff ................
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400800d0: ffffffff ffffffff ffffffff ffffffff ................
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400800e0: ffffffff ffffffff ffffffff ffffffff ................
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400800f0: ffffffff ffffffff ffffffff ffffffff ................
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=> md 400c0000
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400c0000: ffffffff ffffffff ffffffff ffffffff ................
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400c0010: ffffffff ffffffff ffffffff ffffffff ................
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400c0020: ffffffff ffffffff ffffffff ffffffff ................
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400c0030: ffffffff ffffffff ffffffff ffffffff ................
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400c0040: ffffffff ffffffff ffffffff ffffffff ................
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400c0050: ffffffff ffffffff ffffffff ffffffff ................
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400c0060: ffffffff ffffffff ffffffff ffffffff ................
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400c0070: ffffffff ffffffff ffffffff ffffffff ................
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400c0080: ffffffff ffffffff ffffffff ffffffff ................
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400c0090: ffffffff ffffffff ffffffff ffffffff ................
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400c00a0: ffffffff ffffffff ffffffff ffffffff ................
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400c00b0: ffffffff ffffffff ffffffff ffffffff ................
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400c00c0: ffffffff ffffffff ffffffff ffffffff ................
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400c00d0: ffffffff ffffffff ffffffff ffffffff ................
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400c00e0: ffffffff ffffffff ffffffff ffffffff ................
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400c00f0: ffffffff ffffffff ffffffff ffffffff ................
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=>
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------------------------------------------------------------------------------
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The following sequence was performed to test the Flash programming commands:
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------------------------------------------------------------------------------
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=> erase 40080000 400bffff
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Erase Flash from 0x40080000 to 0x400bffff
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.. done
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Erased 1 sectors
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=> cp 0 40080000 10
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Copy to Flash... done
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=> md 0
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00000000: 00000000 00000104 61100200 01000000 ........a.......
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00000010: 00000000 00000000 81140000 82000100 ................
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00000020: 01080000 00004000 22800000 00000600 ......@.".......
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00000030: 00200800 00000000 10000100 00008000 . ..............
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00000040: 00812000 00000200 00020000 80000000 .. .............
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00000050: 00028001 00001000 00040400 00000200 ................
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00000060: 20480000 00000000 20090000 00142000 H...... ..... .
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00000070: 00000000 00004000 24210000 10000000 ......@.$!......
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00000080: 02440002 10000000 00200008 00000000 .D....... ......
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00000090: 02440900 00000000 30a40000 00004400 .D......0.....D.
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000000a0: 04420800 00000000 00000040 00020000 .B.........@....
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000000b0: 05020000 00100000 00060000 00000000 ................
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000000c0: 00400000 00000000 00080000 00040000 .@..............
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000000d0: 10400000 00800004 00000000 00000200 .@..............
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000000e0: 80890000 00010004 00080000 00000020 ...............
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000000f0: 08000000 10000000 00010000 00000000 ................
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=> md 40080000
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40080000: 00000000 00000104 61100200 01000000 ........a.......
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40080010: 00000000 00000000 81140000 82000100 ................
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40080020: 01080000 00004000 22800000 00000600 ......@.".......
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40080030: 00200800 00000000 10000100 00008000 . ..............
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40080040: ffffffff ffffffff ffffffff ffffffff ................
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40080050: ffffffff ffffffff ffffffff ffffffff ................
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40080060: ffffffff ffffffff ffffffff ffffffff ................
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40080070: ffffffff ffffffff ffffffff ffffffff ................
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40080080: ffffffff ffffffff ffffffff ffffffff ................
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40080090: ffffffff ffffffff ffffffff ffffffff ................
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400800a0: ffffffff ffffffff ffffffff ffffffff ................
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400800b0: ffffffff ffffffff ffffffff ffffffff ................
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400800c0: ffffffff ffffffff ffffffff ffffffff ................
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400800d0: ffffffff ffffffff ffffffff ffffffff ................
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400800e0: ffffffff ffffffff ffffffff ffffffff ................
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400800f0: ffffffff ffffffff ffffffff ffffffff ................
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=>
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------------------------------------------------------------------------------
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The following sequence was performed to test storage of the environment
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variables in Flash:
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------------------------------------------------------------------------------
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=> setenv foo bar
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=> saveenv
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Un-Protected 1 sectors
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Erasing Flash...
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.. done
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Erased 1 sectors
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Saving Environment to Flash...
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Protected 1 sectors
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=> reset
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...
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=> printenv
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bootdelay=CONFIG_BOOTDELAY
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baudrate=9600
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ipaddr=192.168.4.7
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serverip=192.168.4.1
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ethaddr=66:55:44:33:22:11
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foo=bar
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stdin=serial
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stdout=serial
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stderr=serial
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Environment size: 170/262140 bytes
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=>
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------------------------------------------------------------------------------
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The following sequence was performed to test image download and run over
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Ethernet interface (both interfaces were tested):
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------------------------------------------------------------------------------
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=> tftpboot 40000 hello_world.bin
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ARP broadcast 1
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TFTP from server 192.168.2.2; our IP address is 192.168.2.7
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Filename 'hello_world.bin'.
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Load address: 0x40000
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Loading: #############
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done
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Bytes transferred = 65912 (10178 hex)
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=> go 40004
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## Starting application at 0x00040004 ...
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Hello World
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argc = 1
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argv[0] = "40004"
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argv[1] = "<NULL>"
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Hit any key to exit ...
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## Application terminated, rc = 0x0
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=>
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------------------------------------------------------------------------------
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The following sequence was performed to test eeprom read/write commands:
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------------------------------------------------------------------------------
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=> md 40000
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00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
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00040010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
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00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x
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00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
|
||||
00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x
|
||||
00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..!
|
||||
00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L
|
||||
00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@.......
|
||||
00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{..
|
||||
00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@...
|
||||
000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|...
|
||||
000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|...
|
||||
000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L
|
||||
000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L
|
||||
000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..!
|
||||
000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a..
|
||||
=> eeprom write 40000 0 40
|
||||
|
||||
EEPROM write: addr 00040000 off 0000 count 64 ... done
|
||||
=> mw 50000 0 1000
|
||||
=> eeprom read 50000 0 40
|
||||
|
||||
EEPROM read: addr 00050000 off 0000 count 64 ... done
|
||||
=> md 50000
|
||||
00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a..
|
||||
00050010: 90010024 48000005 7fc802a6 801effe8 ...$H...........
|
||||
00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x
|
||||
00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`..
|
||||
00050040: 00000000 00000000 00000000 00000000 ................
|
||||
00050050: 00000000 00000000 00000000 00000000 ................
|
||||
00050060: 00000000 00000000 00000000 00000000 ................
|
||||
00050070: 00000000 00000000 00000000 00000000 ................
|
||||
00050080: 00000000 00000000 00000000 00000000 ................
|
||||
00050090: 00000000 00000000 00000000 00000000 ................
|
||||
000500a0: 00000000 00000000 00000000 00000000 ................
|
||||
000500b0: 00000000 00000000 00000000 00000000 ................
|
||||
000500c0: 00000000 00000000 00000000 00000000 ................
|
||||
000500d0: 00000000 00000000 00000000 00000000 ................
|
||||
000500e0: 00000000 00000000 00000000 00000000 ................
|
||||
000500f0: 00000000 00000000 00000000 00000000 ................
|
||||
=>
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Patch per Mon, 06 Aug 2001 17:57:27:
|
||||
|
||||
- upgraded Flash support (added support for the following chips:
|
||||
AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B)
|
||||
- BCR tweakage for the 8260 bus mode
|
||||
- SIUMCR tweakage enabling the MI interrupt (IRQ7)
|
||||
|
||||
To simplify switching between the bus modes, a new configuration
|
||||
option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h"
|
||||
file. If it is defined, BCR will be configured for the 60x mode,
|
||||
otherwise - for the 8260 mode.
|
||||
|
||||
Concerning the SIUMCR modification: it's hard to predict whether it
|
||||
will induce any problems on the other (60x mode) board. However, the
|
||||
problems (if they appear) should be easy to notice - if the board
|
||||
does not boot, it's most likely caused by the DPPC configuration in
|
||||
SIUMCR.
|
||||
|
|
@ -1,352 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc8260.h>
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
|
||||
/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
|
||||
/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
|
||||
/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
|
||||
/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
|
||||
/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
|
||||
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||
/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||
/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||
/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||
/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||
/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||
/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||
/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||
/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
|
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
|
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
|
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
|
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
|
||||
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
|
||||
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
|
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
|
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
|
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
|
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
|
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
|
||||
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
|
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
|
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
|
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
|
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
|
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
|
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
|
||||
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
|
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
|
||||
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
|
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
||||
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
#if defined(CONFIG_SYS_I2C_SOFT)
|
||||
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
|
||||
#else
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#else /* normal I/O port pins */
|
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#endif
|
||||
#endif
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
if (i < 0 || strncmp(buf, "TQM82", 5)) {
|
||||
puts ("### No HW ID - assuming TQM8260\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
puts (buf);
|
||||
putc ('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
|
||||
*
|
||||
* This routine performs standard 8260 initialization sequence
|
||||
* and calculates the available memory size. It may be called
|
||||
* several times to try different SDRAM configurations on both
|
||||
* 60x and local buses.
|
||||
*/
|
||||
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||
ulong orx, volatile uchar * base)
|
||||
{
|
||||
volatile uchar c = 0xff;
|
||||
volatile uint *sdmr_ptr;
|
||||
volatile uint *orx_ptr;
|
||||
ulong maxsize, size;
|
||||
int i;
|
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be
|
||||
* mapped by the controller. That means, that the initial mapping has
|
||||
* to be (at least) twice as large as the maximum expected size.
|
||||
*/
|
||||
maxsize = (1 + (~orx | 0x7fff)) / 2;
|
||||
|
||||
/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
|
||||
* we are configuring CS1 if base != 0
|
||||
*/
|
||||
sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
|
||||
orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
|
||||
|
||||
*orx_ptr = orx;
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
|
||||
*(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*base = c;
|
||||
|
||||
size = get_ram_size((long *)base, maxsize);
|
||||
*orx_ptr = orx | ~(size - 1);
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
long size8, size9;
|
||||
#endif
|
||||
long psize, lsize;
|
||||
|
||||
psize = 16 * 1024 * 1024;
|
||||
lsize = 0;
|
||||
|
||||
memctl->memc_psrt = CONFIG_SYS_PSRT;
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
#if 0 /* Just for debugging */
|
||||
#define prt_br_or(brX,orX) do { \
|
||||
ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
|
||||
ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
|
||||
printf ("\n" \
|
||||
#brX " 0x%08x " #orX " 0x%08x " \
|
||||
"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
|
||||
memctl->memc_ ## brX, memctl->memc_ ## orX, \
|
||||
start, start+sizem, (sizem+1)>>20); \
|
||||
} while (0)
|
||||
prt_br_or (br0, or0);
|
||||
prt_br_or (br1, or1);
|
||||
prt_br_or (br2, or2);
|
||||
prt_br_or (br3, or3);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* 60x SDRAM setup:
|
||||
*/
|
||||
size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
|
||||
if (size8 < size9) {
|
||||
psize = size9;
|
||||
printf ("(60x:9COL - %ld MB, ", psize >> 20);
|
||||
} else {
|
||||
psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
|
||||
(uchar *) CONFIG_SYS_SDRAM_BASE);
|
||||
printf ("(60x:8COL - %ld MB, ", psize >> 20);
|
||||
}
|
||||
|
||||
/* Local SDRAM setup:
|
||||
*/
|
||||
#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
|
||||
memctl->memc_lsrt = CONFIG_SYS_LSRT;
|
||||
size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
|
||||
if (size8 < size9) {
|
||||
lsize = size9;
|
||||
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
|
||||
} else {
|
||||
lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
|
||||
(uchar *) SDRAM_BASE2_PRELIM);
|
||||
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Set up BR2 so that the local SDRAM goes
|
||||
* right after the 60x SDRAM
|
||||
*/
|
||||
memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
|
||||
(CONFIG_SYS_SDRAM_BASE + psize);
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
icache_enable ();
|
||||
|
||||
return (psize);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8255,300MHz"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,266MHz"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,L2_CACHE,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="MPC8265,300MHz,BUSMODE_60x"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_TQM8260=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
TQM8260 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
|
||||
IDS8247 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
|
||||
HWW1U1A powerpc mpc85xx - - Kyle Moffett <Kyle.D.Moffett@boeing.com>
|
||||
hymod powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
|
||||
|
|
|
|||
|
|
@ -1,620 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Imported from global configuration:
|
||||
* CONFIG_MPC8255
|
||||
* CONFIG_MPC8265
|
||||
* CONFIG_200MHz
|
||||
* CONFIG_266MHz
|
||||
* CONFIG_300MHz
|
||||
* CONFIG_L2_CACHE
|
||||
* CONFIG_BUSMODE_60x
|
||||
*/
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000
|
||||
|
||||
|
||||
#if 0
|
||||
#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
|
||||
#else
|
||||
#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"bootfile=tqm8260/uImage\0" \
|
||||
"kernel_addr=400C0000\0" \
|
||||
"ramdisk_addr=40240000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
|
||||
/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
|
||||
#if (CONFIG_TQM8260 <= 100)
|
||||
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00020000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
|
||||
#define I2C_READ ((iop->pdat & 0x00020000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
#else
|
||||
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_I2C_X
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/
|
||||
#ifdef CONFIG_82xx_CONS_SMC1
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
#endif
|
||||
#ifdef CONFIG_82xx_CONS_SMC2
|
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
|
||||
#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
|
||||
#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
|
||||
*
|
||||
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
|
||||
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
|
||||
|
||||
/*
|
||||
* - RX clk is CLK11
|
||||
* - TX clk is CLK12
|
||||
*/
|
||||
# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
|
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13
|
||||
* - Tx-CLK is CLK14
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Full Duplex in FSMR
|
||||
*/
|
||||
# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
|
||||
# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
|
||||
# define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
|
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
||||
#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
|
||||
# define CONFIG_8260_CLKIN 66666666 /* in Hz */
|
||||
#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
|
||||
# ifndef CONFIG_300MHz
|
||||
# define CONFIG_8260_CLKIN 66666666 /* in Hz */
|
||||
# else
|
||||
# define CONFIG_8260_CLKIN 83333000 /* in Hz */
|
||||
# endif
|
||||
#endif /* CONFIG_MPC8255 */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
|
||||
* The main FLASH is whichever is connected to *CS0.
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH0_BASE 0x40000000
|
||||
#define CONFIG_SYS_FLASH1_BASE 0x60000000
|
||||
#define CONFIG_SYS_FLASH0_SIZE 32
|
||||
#define CONFIG_SYS_FLASH1_SIZE 32
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
/* use CFI flash driver */
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO 1
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SIZE 0x08000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block
|
||||
*/
|
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
|
||||
*/
|
||||
#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
|
||||
|
||||
#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
|
||||
# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
|
||||
#else /* ! MPC8255 && !MPC8265 */
|
||||
# if defined(CONFIG_266MHz)
|
||||
# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
|
||||
# elif defined(CONFIG_300MHz)
|
||||
# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
|
||||
# else
|
||||
# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__)
|
||||
# endif
|
||||
#endif /* CONFIG_MPC8255 */
|
||||
|
||||
/* no slaves so just fill with zeros */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*
|
||||
* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
|
||||
* is mapped at SDRAM_BASE2_PRELIM.
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
|
||||
HID0_IFEM|HID0_ABE)
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#ifdef CONFIG_BUSMODE_60x
|
||||
#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
|
||||
BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
|
||||
#else
|
||||
#define BCR_APD01 0x10000000
|
||||
#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if 0
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
|
||||
#else
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
* Ensure DFBRG is Divide by 16
|
||||
*/
|
||||
#define CONFIG_SYS_SCCR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
* 2 Local SDRAM 32 bit SDRAM
|
||||
*
|
||||
*/
|
||||
|
||||
/* Initialize SDRAM on local bus
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_LOCAL_SDRAM
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
|
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2]
|
||||
*/
|
||||
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
|
||||
#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x4000
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command
|
||||
*-----------------------------------------------------------------------------
|
||||
* In fact, the address is rather configuration data presented to the SDRAM on
|
||||
* its address lines. Because the address lines may be mux'ed externally either
|
||||
* for 8 column or 9 column devices, some bits appear twice in the 8260's
|
||||
* address:
|
||||
*
|
||||
* | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
|
||||
* | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
|
||||
* 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
|
||||
* 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
|
||||
* Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_MRS_OFFS 0x00000110
|
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/
|
||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX)
|
||||
|
||||
/* SDRAM on TQM8260 can have either 8 or 9 columns.
|
||||
* The number affects configuration values.
|
||||
*/
|
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
*/
|
||||
#define CONFIG_SYS_PSRT 0x20
|
||||
#define CONFIG_SYS_LSRT 0x20
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
|
||||
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/
|
||||
#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A7 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/
|
||||
#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A5 |\
|
||||
ORxS_NUMR_13)
|
||||
|
||||
#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A7 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
/* Bank 2 - Local bus SDRAM
|
||||
*/
|
||||
#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
|
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
|
||||
|
||||
#define SDRAM_BASE2_PRELIM 0x80000000
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/
|
||||
#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A8 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/
|
||||
#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A6 |\
|
||||
ORxS_NUMR_13)
|
||||
|
||||
#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
|
||||
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue