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ARM: AM43xx: Fix UART clocks enabling

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After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2014-06-02 10:49:03 +05:30 committed by Tom Rini
parent fa03834fdf
commit ccd2f8db81
1 changed files with 9 additions and 0 deletions
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9
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
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@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
void setup_clocks_for_console(void)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(&cmwkup->wkup_uart0ctrl);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
}
}
void enable_basic_clocks(void)