diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 22212c2202..179e39d80e 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -15,6 +15,7 @@ #define CCM_CCGR4 0x020C4078 #define CCM_CCGR5 0x020C407c #define CCM_CCGR6 0x020C4080 +#define CCM_CBCMR 0x020c4018 #define PMU_MISC2 0x020C8170 diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 12c30d274f..9894a880fb 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -468,6 +468,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, #endif /* CONFIG_SPL_BUILD */ +#define MX6_MMDC_MDSCR_CON_REQ 0x00008000 + #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 #define MX6_MMDC_P0_MDOTC 0x021b0008 diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h index c3c4d69818..3ffd9200dd 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h @@ -42,4 +42,15 @@ #define MX6_IOM_DRAM_SDWE_B 0x020e0354 +#define MX6_IOM_GRP_ADDDS 0x020e05ac +#define MX6_IOM_GRP_CTLDS 0x020e05c8 +#define MX6_IOM_GRP_DDRMODE 0x020e05c0 +#define MX6_IOM_GRP_DDRPKE 0x020e05b4 +#define MX6_IOM_GRP_DDRMODE_CTL 0x020e05b0 +#define MX6_IOM_GRP_DDR_TYPE 0x020e05d0 +#define MX6_IOM_GRP_B0DS 0x020e05c4 +#define MX6_IOM_GRP_B1DS 0x020e05cc +#define MX6_IOM_GRP_B2DS 0x020e05d4 +#define MX6_IOM_GRP_B3DS 0x020e05d8 + #endif /*__ASM_ARCH_MX6SL_DDR_H__ */ diff --git a/board/reMarkable/zero-gravitas/imximage.cfg b/board/reMarkable/zero-gravitas/imximage.cfg index 392f9aea9d..eb4f51ea7b 100644 --- a/board/reMarkable/zero-gravitas/imximage.cfg +++ b/board/reMarkable/zero-gravitas/imximage.cfg @@ -1,5 +1,11 @@ /* Copyright (C) 2016 The Magma Company AS */ +#define CONFIG_MX6SL 1 +/* Avoid C declarations, we only want defines */ +#undef CONFIG_SPL_BUILD +#define __ASSEMBLY__ +#include +#include /* image version */ @@ -25,52 +31,71 @@ BOOT_FROM sd */ /* =============================================================================*/ -/* Enable all clocks (they are disabled by ROM code*/ +/* Enable all clocks, they are disabled by ROM code */ /* =============================================================================*/ /* CCGR0; CAAM */ -DATA 4 0x020c4068 0xffffffff +DATA 4 CCM_CCGR0 0xffffffff /* CCGR1; I2C4, SPI, ENET */ -DATA 4 0x020c406c 0xffffffff +DATA 4 CCM_CCGR1 0xffffffff /* CCGR2; I2C1, I2C2, I2C3, LCDIF, OCOTP, GPMI */ -DATA 4 0x020c4070 0xffffffff +DATA 4 CCM_CCGR2 0xffffffff /* CCGR3; ENET, LCDIF, QSPI 0, IPU 0 */ -DATA 4 0x020c4074 0xffffffff +DATA 4 CCM_CCGR3 0xffffffff /* CCGR4; GPMI, PCIE, QSPI 1 */ -DATA 4 0x020c4078 0xffffffff +DATA 4 CCM_CCGR4 0xffffffff /* CCGR5; UART, SATA */ -DATA 4 0x020c407c 0xffffffff +DATA 4 CCM_CCGR5 0xffffffff /* CCGR6; USDHC, IPU, USBOH3, CAAM EMI slow clock */ -DATA 4 0x020c4080 0xffffffff +DATA 4 CCM_CCGR6 0xffffffff /* ????; seems to be in several DCDs as well in the DDR script aid */ -/* Might be General Purpose Timer #0 Controller (USB_UOG1_GPTIMER0CTRL) */ -/* However, the absolute address is wrong in that case, might be some offset */ -DATA 4 0x020c4084 0xffffffff +/* It is CCGR7 in imx5, not defined in i.MX6SL manual */ +/* DATA 4 0x020c4084 0xffffffff */ /* DDR clk to 400MHz */ /* CCM Bus Clock Multiplexer Register (CCM_CBCMR) in reference manual */ -DATA 4 0x020c4018 0x00260324 +DATA 4 CCM_CBCMR 0x00260324 /* =============================================================================*/ -/* IOMUX*/ +/* IOMUX: Set up pins for memory controller */ /* =============================================================================*/ /* DDR IO TYPE:*/ -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE*/ -/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE*/ -DATA 4 0x020e05c0 0x00020000 -DATA 4 0x020e05b4 0x00000000 +/* Bit 17: DDR / CMOS Input Mode Field + Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04, + DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09, + DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, + DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19, + DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24, + DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, + DRAM_DATA30, DRAM_DATA31 + 0 CMOS — CMOS input mode. + 1 DIFFERENTIAL — Differential input mode.*/ +DATA 4 MX6_IOM_GRP_DDRMODE 0x00020000 /* Select differential mode */ + +/* Bit 12: Pull / Keep Enable Field + Affected pads: DRAM_DATA00, DRAM_DATA01, DRAM_DATA02, DRAM_DATA03, DRAM_DATA04, + DRAM_DATA05, DRAM_DATA06, DRAM_DATA07, DRAM_DATA08, DRAM_DATA09, + DRAM_DATA10, DRAM_DATA11, DRAM_DATA12, DRAM_DATA13, DRAM_DATA14, + DRAM_DATA15, DRAM_DATA16, DRAM_DATA17, DRAM_DATA18, DRAM_DATA19, + DRAM_DATA20, DRAM_DATA21, DRAM_DATA22, DRAM_DATA23, DRAM_DATA24, + DRAM_DATA25, DRAM_DATA26, DRAM_DATA27, DRAM_DATA28, DRAM_DATA29, + DRAM_DATA30, DRAM_DATA31 + 0 DISABLED — Pull/Keeper Disabled + 1 ENABLED — Pull/Keeper Enabled */ +DATA 4 MX6_IOM_GRP_DDRPKE 0x00000000 /* Disable pull/keeper */ /* CLOCK:*/ -/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0*/ -DATA 4 0x020e0338 0x00000030 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ +/* Don't bother setting it, 0x00000030 is the default value */ +/* DATA 4 MX6_IOM_DRAM_SDCLK0_P 0x00000030 */ /* Control:*/ @@ -81,24 +106,24 @@ DATA 4 0x020e0338 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS*/ /* IOMUXC_SW_PAD_CTL_GRP_CTLDS*/ -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e031c 0x00000030 -DATA 4 0x020e0320 0x00000030 -DATA 4 0x020e032c 0x00000000 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05c8 0x00000030 +DATA 4 MX6_IOM_DRAM_CAS_B 0x00000030 +DATA 4 MX6_IOM_DRAM_RAS_B 0x00000030 +DATA 4 MX6_IOM_DRAM_RESET 0x00000030 +DATA 4 MX6_IOM_DRAM_SDBA2 0x00000000 +DATA 4 MX6_IOM_GRP_ADDDS 0x00000030 +DATA 4 MX6_IOM_GRP_CTLDS 0x00000030 /* Data Strobes:*/ -/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL*/ +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL ?? IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3*/ -DATA 4 0x020e05b0 0x00020000 -DATA 4 0x020e0344 0x00000030 -DATA 4 0x020e0348 0x00000030 -DATA 4 0x020e034c 0x00000030 -DATA 4 0x020e0350 0x00000030 +DATA 4 MX6_IOM_GRP_DDRMODE_CTL 0x00020000 +DATA 4 MX6_IOM_DRAM_SDQS0_P 0x00000030 +DATA 4 MX6_IOM_DRAM_SDQS1_P 0x00000030 +DATA 4 MX6_IOM_DRAM_SDQS2_P 0x00000030 +DATA 4 MX6_IOM_DRAM_SDQS3_P 0x00000030 /* Data:*/ @@ -108,46 +133,47 @@ DATA 4 0x020e0350 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B2DS*/ /* IOMUXC_SW_PAD_CTL_GRP_B3DS*/ -DATA 4 0x020e05d0 0x000C0000 -DATA 4 0x020e05c4 0x00000030 -DATA 4 0x020e05cc 0x00000030 -DATA 4 0x020e05d4 0x00000030 -DATA 4 0x020e05d8 0x00000030 +DATA 4 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +DATA 4 MX6_IOM_GRP_B0DS 0x00000030 +DATA 4 MX6_IOM_GRP_B1DS 0x00000030 +DATA 4 MX6_IOM_GRP_B2DS 0x00000030 +DATA 4 MX6_IOM_GRP_B3DS 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2*/ /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3*/ -DATA 4 0x020e030c 0x00000030 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0318 0x00000030 +DATA 4 MX6_IOM_DRAM_DQM0 0x00000030 +DATA 4 MX6_IOM_DRAM_DQM1 0x00000030 +DATA 4 MX6_IOM_DRAM_DQM2 0x00000030 +DATA 4 MX6_IOM_DRAM_DQM3 0x00000030 + +/* ============================================================================= */ +/* DDR Controller Registers */ +/* ============================================================================= */ +/* Manufacturer: Micron */ +/* Device Part Number: MT41J128M16HA-187E */ +/* Clock Freq.: 400MHz */ +/* Density per CS in Gb: 4 */ +/* Chip Selects used: 2 */ +/* Total DRAM density (Gb) 8 */ +/* Number of Banks: 8 */ +/* Row address: 14 */ +/* Column address: 10 */ +/* Data bus width 32 */ +/* ============================================================================= */ -/* =============================================================================*/ -/* DDR Controller Registers*/ -/* =============================================================================*/ -/* Manufacturer: Micron*/ -/* Device Part Number: MT41J128M16HA-187E*/ -/* Clock Freq.: 400MHz*/ -/* Density per CS in Gb: 4*/ -/* Chip Selects used: 2*/ -/* Total DRAM density (Gb) 8*/ -/* Number of Banks: 8*/ -/* Row address: 14*/ -/* Column address: 10*/ -/* Data bus width 32*/ -/* =============================================================================*/ /* DDR_PHY_P0_MPZQHWCTRL: enable both one-time & periodic HW ZQ calibration.*/ /* change ZQ_HW_PER=256ms: Original - 0xa1390003*/ -DATA 4 0x021b0800 0xa1390023 +DATA 4 MX6_MMDC_P0_MPZQHWCTRL 0xa1390023 /* write leveling: based on Freescale board layout and T topology*/ /* For target board: may need to run write leveling calibration*/ /* to fine tune these settings*/ /* If target board does not use T topology: then these registers*/ /* should either be cleared or write leveling calibration can be run*/ -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F +DATA 4 MX6_MMDC_P0_MPWLDECTRL0 0x002D0028 +DATA 4 MX6_MMDC_P0_MPWLDECTRL1 0x00280028 /* ######################################################*/ /* calibration values based on calibration compare of 0x00ffff00:*/ @@ -159,25 +185,34 @@ DATA 4 0x021b0810 0x001F001F /* MPDGCTRL1 PHY0*/ /* MPRDDLCTL PHY0*/ /* MPWRDLCTL PHY0*/ -DATA 4 0x021b083c 0x407E007F -DATA 4 0x021b0840 0x00690069 -DATA 4 0x021b0848 0x42424645 -DATA 4 0x021b0850 0x3B383630 +/*DATA 4 MX6_MMDC_P0_MPDGCTRL0 0x407E007F*/ +/*DATA 4 MX6_MMDC_P0_MPDGCTRL1 0x00690069*/ +/* Read DQS gating calibration */ +DATA 4 MX6_MMDC_P0_MPDGCTRL0 0x420C0204 +DATA 4 MX6_MMDC_P0_MPDGCTRL1 0x01700168 + +/* DATA 4 MX6_MMDC_P0_MPRDDLCTL 0x42424645 */ +/* DATA 4 MX6_MMDC_P0_MPWRDLCTL 0x3B383630 */ + +/* Read calibration */ +DATA 4 MX6_MMDC_P0_MPRDDLCTL 0x3E3E4446 +/* Write calibration */ +DATA 4 MX6_MMDC_P0_MPWRDLCTL 0x38343830 /* DDR_PHY_P0_MPREDQBY0DL3*/ /* DDR_PHY_P0_MPREDQBY1DL3*/ /* DDR_PHY_P0_MPREDQBY2DL3*/ /* DDR_PHY_P0_MPREDQBY3DL3*/ -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 +DATA 4 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +DATA 4 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +DATA 4 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +DATA 4 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 /* Complete calibration by forced measurement:*/ /* DDR_PHY_P0_MPMUR0: frc_msr*/ -DATA 4 0x021b08b8 0x00000800 +DATA 4 MX6_MMDC_P0_MPMUR0 0x00000800 /* MMDC0_MDPDC*/ /* MMDC0_MDOTC*/ @@ -185,54 +220,78 @@ DATA 4 0x021b08b8 0x00000800 /* MMDC0_MDCFG1*/ /* MMDC0_MDCFG2*/ /* MMDC0_MDMISC*/ -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0008 0x00333040 -DATA 4 0x021b000c 0x3F435313 -DATA 4 0x021b0010 0xB68E8B63 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b0018 0x00081740 +DATA 4 MX6_MMDC_P0_MDPDC 0x00020024 +DATA 4 MX6_MMDC_P0_MDOTC 0x00333040 +DATA 4 MX6_MMDC_P0_MDCFG0 0x3F435313 +DATA 4 MX6_MMDC_P0_MDCFG1 0xB68E8B63 +DATA 4 MX6_MMDC_P0_MDCFG2 0x01FF00DB +DATA 4 MX6_MMDC_P0_MDMISC 0x00091740 -/* MMDC0_MDSCR: set the Configuration request bit during MMDC set up*/ -/* MMDC0_MDRWD; recommend to maintain the default values*/ -/* MMDC0_MDOR*/ -/* CS0_END*/ +/* =============================================================== */ +/* MMDC initialization sequence from 32.4.2 in the i.MX6SL manual */ +/* =============================================================== */ /* MMDC0_MDCTL*/ -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x00431023 -DATA 4 0x021b0040 0x0000004F -DATA 4 0x021b0000 0xC3190000 +/* Set the Configuration request bit during MMDC set up*/ +DATA 4 MX6_MMDC_P0_MDSCR MX6_MMDC_MDSCR_CON_REQ +/* Delay register; recommend to maintain the default values*/ +DATA 4 MX6_MMDC_P0_MDRWD 0x000026d2 +/* Out of reset delay register */ +/* CKE HIGH to a valid command: 0 cycles */ +/* Time from SDE enable to CKE rise: 1 cycle */ +/* In case that DDR reset# is low, will wait */ +/* until it's high and thenwait this period until */ +/* rising CKE. (JEDEC value is 500 us) */ +/* Time from SDE enable to DDR reset# high: 14 cycles */ +DATA 4 MX6_MMDC_P0_MDOR 0x00431023 +/* CS0_END. Defines the absolute last address */ +/* associated with CS0 with increments of 256Mb. */ +/* CS0_END=AXI_ADDRESS[31:25] bits. */ +/* MMDC0_MDASP[CS0_END] should be set to */ +/* DDR_CS_SIZE/32M + 0x3f (channel 0 base address */ +/* begins at 0x80000000) */ +/* 512MB / 256Mbit => 16 + 0x3F => 0x4F */ +DATA 4 MX6_MMDC_P0_MDASP 0x0000004F +/*DATA 4 MX6_MMDC_P0_MDASP 0x0000004F*/ + +/*DATA 4 MX6_MMDC_P0_MDCTL 0xC3190000*/ +DATA 4 MX6_MMDC_P0_MDCTL 0x83190000 /* Mode register writes*/ -/* MMDC0_MDSCR: MR2 write: CS0*/ /* MMDC0_MDSCR: MR3 write: CS0*/ /* MMDC0_MDSCR: MR1 write: CS0*/ /* MMDC0_MDSCR: MR0 write: CS0*/ -/* MMDC0_MDSCR: ZQ calibration command sent to device on CS0*/ -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00048031 -DATA 4 0x021b001c 0x05208030 -DATA 4 0x021b001c 0x04008040 + +/* MMDC0_MDSCR: MR2 write: Bank 0, CS0 + Load Mode Register Command + DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB)*/ +DATA 4 MX6_MMDC_P0_MDSCR 0x02008032 +/*DATA 4 MX6_MMDC_P0_MDSCR 0x04008032*/ +DATA 4 MX6_MMDC_P0_MDSCR 0x00008033 +DATA 4 MX6_MMDC_P0_MDSCR 0x00048031 +DATA 4 MX6_MMDC_P0_MDSCR 0x05208030 +/* MMDC0_MDSCR: ZQ calibration command sent to device on CS0 */ +DATA 4 MX6_MMDC_P0_MDSCR 0x04008040 /* MMDC0_MDSCR: MR2 write: CS1*/ /* MMDC0_MDSCR: MR3 write: CS1*/ /* MMDC0_MDSCR: MR1 write: CS1*/ /* MMDC0_MDSCR: MR0 write: CS1*/ -/* MMDC0_MDSCR: ZQ calibration command sent to device on CS1*/ -DATA 4 0x021b001c 0x0400803A -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00048039 -DATA 4 0x021b001c 0x05208038 -DATA 4 0x021b001c 0x04008048 +/* FIXME: these stop the board when run a second time, we only use one CS? */ +/* DATA 4 MX6_MMDC_P0_MDSCR 0x0400803A */ +/* DATA 4 MX6_MMDC_P0_MDSCR 0x0000803B */ +/* DATA 4 MX6_MMDC_P0_MDSCR 0x00048039 */ +/* DATA 4 MX6_MMDC_P0_MDSCR 0x05208038 */ +/* MMDC0_MDSCR: ZQ calibration command sent to device on CS1 */ +/* DATA 4 MX6_MMDC_P0_MDSCR 0x04008048 */ /* MMDC0_MDREF*/ /* DDR_PHY_P0_MPODTCTRL*/ -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00011117 +DATA 4 MX6_MMDC_P0_MDREF 0x00005800 +/*DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00011117*/ +DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00022227 @@ -240,7 +299,7 @@ DATA 4 0x021b0818 0x00011117 /* MMDC0_MAPSR ADOPT power down enabled*/ /* MMDC0_MDSCR: clear this register (especially the configuration bit as initialization is complete*/ -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 +DATA 4 MX6_MMDC_P0_MDPDC 0x00025564 +DATA 4 MX6_MMDC_P0_MAPSR 0x00011006 +DATA 4 MX6_MMDC_P0_MDSCR 0x00000000