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@ -10,9 +10,28 @@
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/fsl_memac.h>
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#include <fsl_memac.h>
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#include <fm_eth.h>
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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#define memac_out_32(a, v) out_le32(a, v)
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#define memac_clrbits_32(a, v) clrbits_le32(a, v)
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#define memac_setbits_32(a, v) setbits_le32(a, v)
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#else
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#define memac_out_32(a, v) out_be32(a, v)
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#define memac_clrbits_32(a, v) clrbits_be32(a, v)
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#define memac_setbits_32(a, v) setbits_be32(a, v)
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#endif
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static u32 memac_in_32(u32 *reg)
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{
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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return in_le32(reg);
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#else
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return in_be32(reg);
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#endif
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}
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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@ -28,31 +47,31 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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memac_out_32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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memac_out_32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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@ -75,39 +94,39 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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return 0xffff;
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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memac_out_32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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out_be32(®s->mdio_ctl, mdio_ctl);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return in_be32(®s->mdio_data) & 0xffff;
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return memac_in_32(®s->mdio_data) & 0xffff;
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}
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int memac_mdio_reset(struct mii_dev *bus)
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@ -143,8 +162,9 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
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* like T2080QDS, this bit default is '0', which leads to MDIO failure
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* on XAUI PHY, so set this bit definitely.
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*/
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setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
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MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
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memac_setbits_32(
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&((struct memac_mdio_controller *)info->regs)->mdio_stat,
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MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
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return mdio_register(bus);
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}
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