arm: Use optimized memcpy and memset from linux
Using optimized versions of memset and memcpy from linux brings a quite
noticeable speed (x2 or better) improvement for these two functions.
Here are some numbers for test done with jadecpu
| HEAD(1)| HEAD(1)| HEAD(2)| HEAD(2)|
| | +patch | | +patch |
---------------------------+--------+--------+--------+--------+
Reset to prompt | 438ms | 330ms | 228ms | 120ms |
| | | | |
TFTP a 3MB img | 4782ms | 3428ms | 3245ms | 2820ms |
| | | | |
FATLOAD USB a 3MB img* | 8515ms | 8510ms | ------ | ------ |
| | | | |
BOOTM LZO img in RAM | 3473ms | 3168ms | 592ms | 592ms |
where CRC is | 615ms | 615ms | 54ms | 54ms |
uncompress | 2460ms | 2462ms | 450ms | 451ms |
final boot_elf | 376ms | 68ms | 65ms | 65ms |
| | | | |
BOOTM LZO img in FLASH | 3207ms | 2902ms | 1050ms | 1050ms |
where CRC is | 600ms | 600ms | 135ms | 135ms |
uncompress | 2209ms | 2211ms | 828ms | 828ms |
| | | | |
Copy 1.4MB from NOR to RAM | 134ms | 72ms | 120ms | 70ms |
(1) No dcache
(2) dcache enabled in board_init
*Does not work when dcache is on
Size impact:
C version:
text data bss dec hex filename
202862 18912 266456 488230 77326 u-boot
ASM version:
text data bss dec hex filename
203798 18912 266288 488998 77626 u-boot
222712 u-boot.bin
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
utp
Matthias Weisser
Albert ARIBAUD
parent
b65a77a861
commit
d8834a1323
6
README
6
README
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@ -2944,6 +2944,12 @@ Low Level (hardware related) configuration options:
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that is executed before the actual U-Boot. E.g. when
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compiling a NAND SPL.
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- CONFIG_USE_ARCH_MEMCPY
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CONFIG_USE_ARCH_MEMSET
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If these options are used a optimized version of memcpy/memset will
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be used if available. These functions may be faster under some
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conditions but may increase the binary size.
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Building the Software:
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======================
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@ -0,0 +1,60 @@
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/*
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* arch/arm/include/asm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define pull lsr
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#define push lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define pull lsl
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#define push lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
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defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
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defined(__ARM_ARCH_7R__)
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* Cache alligned
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*/
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#define CALGN(code...) code
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@ -1,6 +1,8 @@
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#ifndef __ASM_ARM_STRING_H
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#define __ASM_ARM_STRING_H
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#include <config.h>
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/*
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* We don't do inline string functions, since the
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* optimised inline asm versions are not small.
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@ -12,7 +14,9 @@ extern char * strrchr(const char * s, int c);
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#undef __HAVE_ARCH_STRCHR
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extern char * strchr(const char * s, int c);
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#undef __HAVE_ARCH_MEMCPY
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#ifdef CONFIG_USE_ARCH_MEMCPY
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#define __HAVE_ARCH_MEMCPY
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#endif
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extern void * memcpy(void *, const void *, __kernel_size_t);
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#undef __HAVE_ARCH_MEMMOVE
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@ -22,7 +26,9 @@ extern void * memmove(void *, const void *, __kernel_size_t);
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extern void * memchr(const void *, int, __kernel_size_t);
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#undef __HAVE_ARCH_MEMZERO
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#undef __HAVE_ARCH_MEMSET
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#ifdef CONFIG_USE_ARCH_MEMSET
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#define __HAVE_ARCH_MEMSET
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#endif
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extern void * memset(void *, int, __kernel_size_t);
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#if 0
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@ -44,6 +44,8 @@ COBJS-y += cache-cp15.o
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endif
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COBJS-y += interrupts.o
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COBJS-y += reset.o
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SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
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SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
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SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
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$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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@ -0,0 +1,241 @@
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/*
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* linux/arch/arm/lib/memcpy.S
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*
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* Author: Nicolas Pitre
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* Created: Sep 28, 2005
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* Copyright: MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/assembler.h>
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#define W(instr) instr
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#define LDR1W_SHIFT 0
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#define STR1W_SHIFT 0
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.macro ldr1w ptr reg abort
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W(ldr) \reg, [\ptr], #4
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.endm
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.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
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.endm
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.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro ldr1b ptr reg cond=al abort
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ldr\cond\()b \reg, [\ptr], #1
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.endm
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.macro str1w ptr reg abort
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W(str) \reg, [\ptr], #4
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.endm
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.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro str1b ptr reg cond=al abort
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str\cond\()b \reg, [\ptr], #1
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.endm
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.macro enter reg1 reg2
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stmdb sp!, {r0, \reg1, \reg2}
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.endm
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.macro exit reg1 reg2
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ldmfd sp!, {r0, \reg1, \reg2}
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.endm
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.text
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/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
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.globl memcpy
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memcpy:
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enter r4, lr
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subs r2, r2, #4
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blt 8f
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ands ip, r0, #3
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PLD( pld [r1, #0] )
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bne 9f
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ands ip, r1, #3
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bne 10f
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1: subs r2, r2, #(28)
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stmfd sp!, {r5 - r8}
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blt 5f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcnes r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, r3 ) @ C gets set
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CALGN( add pc, r4, ip )
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PLD( pld [r1, #0] )
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2: PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 4f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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3: PLD( pld [r1, #124] )
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4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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subs r2, r2, #32
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str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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bge 3b
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PLD( cmn r2, #96 )
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PLD( bge 4b )
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5: ands ip, r2, #28
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rsb ip, ip, #32
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#if LDR1W_SHIFT > 0
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lsl ip, ip, #LDR1W_SHIFT
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#endif
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addne pc, pc, ip @ C is always clear here
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b 7f
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6:
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.rept (1 << LDR1W_SHIFT)
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W(nop)
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.endr
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ldr1w r1, r3, abort=20f
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ldr1w r1, r4, abort=20f
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ldr1w r1, r5, abort=20f
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ldr1w r1, r6, abort=20f
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ldr1w r1, r7, abort=20f
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ldr1w r1, r8, abort=20f
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ldr1w r1, lr, abort=20f
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#if LDR1W_SHIFT < STR1W_SHIFT
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lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
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#elif LDR1W_SHIFT > STR1W_SHIFT
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lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
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#endif
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add pc, pc, ip
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nop
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.rept (1 << STR1W_SHIFT)
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W(nop)
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.endr
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str1w r0, r3, abort=20f
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str1w r0, r4, abort=20f
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str1w r0, r5, abort=20f
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str1w r0, r6, abort=20f
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str1w r0, r7, abort=20f
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str1w r0, r8, abort=20f
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str1w r0, lr, abort=20f
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CALGN( bcs 2b )
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7: ldmfd sp!, {r5 - r8}
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8: movs r2, r2, lsl #31
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ldr1b r1, r3, ne, abort=21f
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ldr1b r1, r4, cs, abort=21f
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ldr1b r1, ip, cs, abort=21f
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str1b r0, r3, ne, abort=21f
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str1b r0, r4, cs, abort=21f
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str1b r0, ip, cs, abort=21f
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exit r4, pc
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9: rsb ip, ip, #4
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cmp ip, #2
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ldr1b r1, r3, gt, abort=21f
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ldr1b r1, r4, ge, abort=21f
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ldr1b r1, lr, abort=21f
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str1b r0, r3, gt, abort=21f
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str1b r0, r4, ge, abort=21f
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subs r2, r2, ip
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str1b r0, lr, abort=21f
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blt 8b
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ands ip, r1, #3
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beq 1b
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10: bic r1, r1, #3
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cmp ip, #2
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ldr1w r1, lr, abort=21f
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beq 17f
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bgt 18f
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.macro forward_copy_shift pull push
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subs r2, r2, #28
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blt 14f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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11: stmfd sp!, {r5 - r9}
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PLD( pld [r1, #0] )
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PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 13f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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12: PLD( pld [r1, #124] )
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13: ldr4w r1, r4, r5, r6, r7, abort=19f
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mov r3, lr, pull #\pull
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subs r2, r2, #32
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ldr4w r1, r8, r9, ip, lr, abort=19f
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orr r3, r3, r4, push #\push
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mov r4, r4, pull #\pull
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orr r4, r4, r5, push #\push
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mov r5, r5, pull #\pull
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orr r5, r5, r6, push #\push
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mov r6, r6, pull #\pull
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orr r6, r6, r7, push #\push
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mov r7, r7, pull #\pull
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orr r7, r7, r8, push #\push
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mov r8, r8, pull #\pull
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orr r8, r8, r9, push #\push
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mov r9, r9, pull #\pull
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orr r9, r9, ip, push #\push
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mov ip, ip, pull #\pull
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orr ip, ip, lr, push #\push
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str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
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bge 12b
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PLD( cmn r2, #96 )
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PLD( bge 13b )
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ldmfd sp!, {r5 - r9}
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14: ands ip, r2, #28
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beq 16f
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15: mov r3, lr, pull #\pull
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ldr1w r1, lr, abort=21f
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subs ip, ip, #4
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orr r3, r3, lr, push #\push
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str1w r0, r3, abort=21f
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bgt 15b
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CALGN( cmp r2, #0 )
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CALGN( bge 11b )
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16: sub r1, r1, #(\push / 8)
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b 8b
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.endm
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forward_copy_shift pull=8 push=24
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17: forward_copy_shift pull=16 push=16
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18: forward_copy_shift pull=24 push=8
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@ -0,0 +1,126 @@
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/*
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* linux/arch/arm/lib/memset.S
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*
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* Copyright (C) 1995-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ASM optimised string functions
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*/
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#include <asm/assembler.h>
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.text
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.align 5
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.word 0
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1: subs r2, r2, #4 @ 1 do we have enough
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blt 5f @ 1 bytes to align with?
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cmp r3, #2 @ 1
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strltb r1, [r0], #1 @ 1
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strleb r1, [r0], #1 @ 1
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strb r1, [r0], #1 @ 1
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add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
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/*
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* The pointer is now aligned and the length is adjusted. Try doing the
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* memset again.
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*/
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.globl memset
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memset:
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ands r3, r0, #3 @ 1 unaligned?
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bne 1b @ 1
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/*
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* we know that the pointer in r0 is aligned to a word boundary.
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*/
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orr r1, r1, r1, lsl #8
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orr r1, r1, r1, lsl #16
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mov r3, r1
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cmp r2, #16
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blt 4f
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#if ! CALGN(1)+0
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/*
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* We need an extra register for this loop - save the return address and
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* use the LR
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*/
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str lr, [sp, #-4]!
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mov ip, r1
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mov lr, r1
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2: subs r2, r2, #64
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stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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stmgeia r0!, {r1, r3, ip, lr}
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bgt 2b
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ldmeqfd sp!, {pc} @ Now <64 bytes to go.
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/*
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* No need to correct the count; we're only testing bits from now on
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*/
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tst r2, #32
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stmneia r0!, {r1, r3, ip, lr}
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stmneia r0!, {r1, r3, ip, lr}
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tst r2, #16
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stmneia r0!, {r1, r3, ip, lr}
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ldr lr, [sp], #4
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#else
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/*
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* This version aligns the destination pointer in order to write
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* whole cache lines at once.
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*/
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|
||||
stmfd sp!, {r4-r7, lr}
|
||||
mov r4, r1
|
||||
mov r5, r1
|
||||
mov r6, r1
|
||||
mov r7, r1
|
||||
mov ip, r1
|
||||
mov lr, r1
|
||||
|
||||
cmp r2, #96
|
||||
tstgt r0, #31
|
||||
ble 3f
|
||||
|
||||
and ip, r0, #31
|
||||
rsb ip, ip, #32
|
||||
sub r2, r2, ip
|
||||
movs ip, ip, lsl #(32 - 4)
|
||||
stmcsia r0!, {r4, r5, r6, r7}
|
||||
stmmiia r0!, {r4, r5}
|
||||
tst ip, #(1 << 30)
|
||||
mov ip, r1
|
||||
strne r1, [r0], #4
|
||||
|
||||
3: subs r2, r2, #64
|
||||
stmgeia r0!, {r1, r3-r7, ip, lr}
|
||||
stmgeia r0!, {r1, r3-r7, ip, lr}
|
||||
bgt 3b
|
||||
ldmeqfd sp!, {r4-r7, pc}
|
||||
|
||||
tst r2, #32
|
||||
stmneia r0!, {r1, r3-r7, ip, lr}
|
||||
tst r2, #16
|
||||
stmneia r0!, {r4-r7}
|
||||
ldmfd sp!, {r4-r7, lr}
|
||||
|
||||
#endif
|
||||
|
||||
4: tst r2, #8
|
||||
stmneia r0!, {r1, r3}
|
||||
tst r2, #4
|
||||
strne r1, [r0], #4
|
||||
/*
|
||||
* When we get here, we've got less than 4 bytes to zero. We
|
||||
* may have an unaligned pointer as well.
|
||||
*/
|
||||
5: tst r2, #2
|
||||
strneb r1, [r0], #1
|
||||
strneb r1, [r0], #1
|
||||
tst r2, #1
|
||||
strneb r1, [r0], #1
|
||||
mov pc, lr
|
||||
Loading…
Reference in New Issue