Sound: WM8994: Support I2S0 channel
This patch modifies the WM8994 codec to support I2S0 channel in codec slave mode Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>utp
Dani Krishna Mohan
Tom Rini
parent
d7884e047d
commit
d981d80d74
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@ -36,8 +36,7 @@ static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
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int error = 0;
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int base;
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node = fdtdec_next_compatible(blob, 0,
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COMPAT_SAMSUNG_EXYNOS5_SOUND);
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node = fdt_path_offset(blob, "i2s");
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if (node <= 0) {
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debug("EXYNOS_SOUND: No node for sound in device tree\n");
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return -1;
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@ -80,6 +79,11 @@ static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
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node, "samsung,i2s-bit-clk-framesize", -1);
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error |= i2s->bfs;
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debug("bfs = %d\n", i2s->bfs);
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i2s->id = fdtdec_get_int(blob, node, "samsung,i2s-id", -1);
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error |= i2s->id;
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debug("id = %d\n", i2s->id);
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if (error == -1) {
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debug("fail to get sound i2s node properties\n");
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return -1;
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@ -92,6 +96,7 @@ static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
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i2s->channels = I2S_CHANNELS;
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i2s->rfs = I2S_RFS;
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i2s->bfs = I2S_BFS;
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i2s->id = 0;
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#endif
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return 0;
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}
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@ -130,10 +135,10 @@ static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
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#endif
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if (!strcmp(codectype, "wm8994")) {
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/* Check the codec type and initialise the same */
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ret = wm8994_init(blob, WM8994_AIF2,
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pi2s_tx->samplingrate,
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(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
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pi2s_tx->bitspersample, pi2s_tx->channels);
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ret = wm8994_init(blob, pi2s_tx->id + 1,
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pi2s_tx->samplingrate,
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(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
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pi2s_tx->bitspersample, pi2s_tx->channels);
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} else if (!strcmp(codectype, "max98095")) {
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ret = max98095_init(blob, pi2s_tx->samplingrate,
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(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
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@ -432,12 +432,12 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
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int ret;
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/* AIF(1/0) register adress offset calculated */
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if (aif)
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if (aif-1)
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offset = 4;
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else
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offset = 0;
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switch (wm8994->sysclk[aif]) {
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switch (wm8994->sysclk[aif-1]) {
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case WM8994_SYSCLK_MCLK1:
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reg1 |= SEL_MCLK1;
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rate = wm8994->mclk[0];
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@ -460,7 +460,7 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
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default:
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debug("%s: Invalid input clock selection [%d]\n",
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__func__, wm8994->sysclk[aif]);
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__func__, wm8994->sysclk[aif-1]);
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return -1;
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}
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@ -470,13 +470,18 @@ static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
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reg1 |= WM8994_AIF1CLK_DIV;
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}
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wm8994->aifclk[aif] = rate;
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wm8994->aifclk[aif-1] = rate;
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ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
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WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
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reg1);
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ret |= wm8994_update_bits(WM8994_CLOCKING_1,
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if (aif == WM8994_AIF1)
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ret |= wm8994_update_bits(WM8994_CLOCKING_1,
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WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
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WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
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else if (aif == WM8994_AIF2)
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ret |= wm8994_update_bits(WM8994_CLOCKING_1,
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WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
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WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
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WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
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@ -536,7 +541,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
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break;
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if (i == ARRAY_SIZE(opclk_divs)) {
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debug("%s frequency divisor not found\n",
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__func__);
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__func__);
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return -1;
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}
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ret = wm8994_update_bits(WM8994_CLOCKING_2,
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@ -554,7 +559,7 @@ static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
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return -1;
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}
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ret |= configure_aif_clock(wm8994, aif_id - 1);
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ret |= configure_aif_clock(wm8994, aif_id);
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if (ret < 0) {
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debug("%s: codec register access error\n", __func__);
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@ -607,6 +612,38 @@ static int wm8994_init_volume_aif2_dac1(void)
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return 0;
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}
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/*
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* Initializes Volume for AIF1 to HP path
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*
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* @returns -1 for error and 0 Success.
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*
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*/
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static int wm8994_init_volume_aif1_dac1(void)
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{
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int ret = 0;
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/* Unmute AIF1DAC */
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ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000);
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
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WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
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WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
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WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
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WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
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/* Head Phone Volume */
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ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
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ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
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if (ret < 0) {
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debug("%s: codec register access error\n", __func__);
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return -1;
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}
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return 0;
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}
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/*
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* Intialise wm8994 codec device
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*
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@ -614,7 +651,8 @@ static int wm8994_init_volume_aif2_dac1(void)
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*
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* @returns -1 for error and 0 Success.
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*/
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static int wm8994_device_init(struct wm8994_priv *wm8994)
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static int wm8994_device_init(struct wm8994_priv *wm8994,
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enum en_audio_interface aif_id)
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{
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const char *devname;
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unsigned short reg_data;
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@ -661,13 +699,30 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
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WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
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/* Power enable for AIF2 and DAC1 */
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
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WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
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WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
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WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
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WM8994_DAC1R_ENA);
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if (aif_id == WM8994_AIF1) {
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2,
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WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
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WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
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WM8994_IN2R_ENA);
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4,
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WM8994_ADCL_ENA | WM8994_ADCR_ENA |
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WM8994_AIF1ADC1R_ENA |
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WM8994_AIF1ADC1L_ENA);
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/* Power enable for AIF1 and DAC1 */
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ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5,
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WM8994_AIF1DACL_ENA |
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WM8994_AIF1DACR_ENA |
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WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
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} else if (aif_id == WM8994_AIF2) {
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/* Power enable for AIF2 and DAC1 */
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ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
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WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
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WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
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WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
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WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
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}
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/* Head Phone Initialisation */
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ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
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WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
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@ -695,35 +750,49 @@ static int wm8994_device_init(struct wm8994_priv *wm8994)
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ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
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WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
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/* Routing AIF2 to DAC1 */
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
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WM8994_AIF2DACL_TO_DAC1L_MASK,
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WM8994_AIF2DACL_TO_DAC1L);
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if (aif_id == WM8994_AIF1) {
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/* Routing AIF1 to DAC1 */
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ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING,
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WM8994_AIF1DAC1L_TO_DAC1L);
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
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WM8994_AIF2DACR_TO_DAC1R_MASK,
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WM8994_AIF2DACR_TO_DAC1R);
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ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING,
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WM8994_AIF1DAC1R_TO_DAC1R);
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/* GPIO Settings for AIF2 */
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/* B CLK */
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ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK ,
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WM8994_GPIO_DIR_OUTPUT |
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WM8994_GPIO_FUNCTION_I2S_CLK);
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/* GPIO Settings for AIF1 */
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ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT
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| WM8994_GPIO_FUNCTION_I2S_CLK
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| WM8994_GPIO_INPUT_DEBOUNCE);
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/* LR CLK */
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ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK,
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WM8994_GPIO_DIR_OUTPUT |
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WM8994_GPIO_FUNCTION_I2S_CLK);
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ret |= wm8994_init_volume_aif1_dac1();
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} else if (aif_id == WM8994_AIF2) {
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/* Routing AIF2 to DAC1 */
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ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
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WM8994_AIF2DACL_TO_DAC1L_MASK,
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WM8994_AIF2DACL_TO_DAC1L);
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/* DATA */
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ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK,
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WM8994_GPIO_DIR_OUTPUT |
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WM8994_GPIO_FUNCTION_I2S_CLK);
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ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
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WM8994_AIF2DACR_TO_DAC1R_MASK,
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WM8994_AIF2DACR_TO_DAC1R);
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/* GPIO Settings for AIF2 */
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/* B CLK */
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ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK ,
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WM8994_GPIO_DIR_OUTPUT);
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/* LR CLK */
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ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK,
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WM8994_GPIO_DIR_OUTPUT);
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/* DATA */
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ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
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WM8994_GPIO_FUNCTION_MASK,
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WM8994_GPIO_DIR_OUTPUT);
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ret |= wm8994_init_volume_aif2_dac1();
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}
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ret |= wm8994_init_volume_aif2_dac1();
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if (ret < 0)
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goto err;
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@ -795,7 +864,7 @@ static int get_codec_values(struct sound_codec_info *pcodec_info,
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return 0;
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}
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/*wm8994 Device Initialisation */
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/* WM8994 Device Initialisation */
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int wm8994_init(const void *blob, enum en_audio_interface aif_id,
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int sampling_rate, int mclk_freq,
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int bits_per_sample, unsigned int channels)
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@ -813,15 +882,15 @@ int wm8994_init(const void *blob, enum en_audio_interface aif_id,
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g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
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wm8994_i2c_init(pcodec_info->i2c_bus);
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if (pcodec_info->codec_type == CODEC_WM_8994)
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if (pcodec_info->codec_type == CODEC_WM_8994) {
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g_wm8994_info.type = WM8994;
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else {
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} else {
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debug("%s: Codec id [%d] not defined\n", __func__,
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pcodec_info->codec_type);
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pcodec_info->codec_type);
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return -1;
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}
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ret = wm8994_device_init(&g_wm8994_info);
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ret = wm8994_device_init(&g_wm8994_info, aif_id);
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if (ret < 0) {
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debug("%s: wm8994 codec chip init failed\n", __func__);
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return ret;
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@ -13,6 +13,7 @@
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#define WM8994_SOFTWARE_RESET 0x00
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#define WM8994_POWER_MANAGEMENT_1 0x01
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#define WM8994_POWER_MANAGEMENT_2 0x02
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#define WM8994_POWER_MANAGEMENT_4 0x04
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#define WM8994_POWER_MANAGEMENT_5 0x05
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#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
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#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
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@ -38,6 +39,7 @@
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#define WM8994_AIF2_CONTROL_2 0x311
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#define WM8994_AIF2_MASTER_SLAVE 0x312
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#define WM8994_AIF2_BCLK 0x313
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#define WM8994_AIF1_DAC_FILTERS_1 0x420
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#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
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#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
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#define WM8994_AIF2_DAC_FILTERS_1 0x520
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@ -45,6 +47,7 @@
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#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
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#define WM8994_DAC1_LEFT_VOLUME 0x610
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#define WM8994_DAC1_RIGHT_VOLUME 0x611
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#define WM8994_GPIO_1 0x700
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#define WM8994_GPIO_3 0x702
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#define WM8994_GPIO_4 0x703
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#define WM8994_GPIO_5 0x704
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@ -82,6 +85,20 @@
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/* OPCLK_ENA */
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#define WM8994_OPCLK_ENA 0x0800
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#define WM8994_TSHUT_ENA 0x4000
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#define WM8994_MIXINL_ENA 0x0200
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#define WM8994_MIXINR_ENA 0x0100
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#define WM8994_IN2L_ENA 0x0080
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#define WM8994_IN2R_ENA 0x0020
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/*
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* R5 (0x04) - Power Management (4)
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*/
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#define WM8994_ADCL_ENA 0x0001
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#define WM8994_ADCR_ENA 0x0002
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#define WM8994_AIF1ADC1R_ENA 0x0100
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#define WM8994_AIF1ADC1L_ENA 0x0200
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/*
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* R5 (0x05) - Power Management (5)
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*/
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@ -91,6 +108,12 @@
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/* AIF2DACR_ENA */
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#define WM8994_AIF2DACR_ENA 0x1000
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#define WM8994_AIF2DACR_ENA_MASK 0x1000
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/* AIF1DACL_ENA */
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#define WM8994_AIF1DACL_ENA 0x0200
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#define WM8994_AIF1DACL_ENA_MASK 0x0200
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/* AIF1DACR_ENA */
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#define WM8994_AIF1DACR_ENA 0x0100
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#define WM8994_AIF1DACR_ENA_MASK 0x0100
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/* DAC1L_ENA */
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#define WM8994_DAC1L_ENA 0x0002
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#define WM8994_DAC1L_ENA_MASK 0x0002
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@ -170,6 +193,9 @@
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/*
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* R520 (0x208) - Clocking (1)
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*/
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/* AIF1DSPCLK_ENA */
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#define WM8994_AIF1DSPCLK_ENA 0x0008
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#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008
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/* AIF2DSPCLK_ENA */
|
||||
#define WM8994_AIF2DSPCLK_ENA 0x0004
|
||||
#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
|
||||
|
|
@ -254,6 +280,8 @@
|
|||
/* AIF2DACL_TO_DAC1L */
|
||||
#define WM8994_AIF2DACL_TO_DAC1L 0x0004
|
||||
#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
|
||||
/* AIF1DAC1L_TO_DAC1L */
|
||||
#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001
|
||||
|
||||
/*
|
||||
* R1538 (0x602) - DAC1 Right Mixer Routing
|
||||
|
|
@ -261,6 +289,8 @@
|
|||
/* AIF2DACR_TO_DAC1R */
|
||||
#define WM8994_AIF2DACR_TO_DAC1R 0x0004
|
||||
#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
|
||||
/* AIF1DAC1R_TO_DAC1R */
|
||||
#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001
|
||||
|
||||
/*
|
||||
* R1552 (0x610) - DAC1 Left Volume
|
||||
|
|
@ -285,11 +315,12 @@
|
|||
* GPIO
|
||||
*/
|
||||
/* OUTPUT PIN */
|
||||
#define WM8994_GPIO_DIR_OUTPUT 0x8000
|
||||
#define WM8994_GPIO_DIR_OUTPUT 0x8000
|
||||
/* GPIO PIN MASK */
|
||||
#define WM8994_GPIO_DIR_MASK 0xFFE0
|
||||
#define WM8994_GPIO_DIR_MASK 0xFFE0
|
||||
/* I2S CLK */
|
||||
#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000
|
||||
#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001
|
||||
#define WM8994_GPIO_INPUT_DEBOUNCE 0x0100
|
||||
/* GPn FN */
|
||||
#define WM8994_GPIO_FUNCTION_MASK 0x001F
|
||||
#define WM8994_GPIO_FUNCTION_MASK 0x001F
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@ struct i2stx_info {
|
|||
unsigned int bitspersample; /* bits per sample */
|
||||
unsigned int channels; /* audio channels */
|
||||
unsigned int base_address; /* I2S Register Base */
|
||||
unsigned int id; /* I2S controller id */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue