imx: mx6ul: support mx6ul 9x9 evk board
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk, the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are: 1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC. 2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk supports 512MB DDR3 3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package. This patch add the following: 1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size() 2. Introduce a macro is_mx6ul_9x9_evk using CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work, so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with mx6ul_14x14_evk. And we have no way to dymaically checking this chip is 9x9 or 14x14. 3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations. POWER related configurations also effect for mx6ul_14x14_evk. But power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk. 4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM configurations. 5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file according to board_rev and board_name. 6. Add TARGET_MX6UL_9X9_EVK Kconfig entry Boot Log: U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53) reading u-boot.img reading u-boot.img U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 41C Reset cause: POR Board: MX6UL 9x9 EVK I2C: ready DRAM: 256 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: FEC1 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>utp
Peng Fan
Stefano Babic
parent
bd8366763c
commit
d9cbb264e8
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@ -104,6 +104,14 @@ config TARGET_MX6SXSABRESD
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select DM
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select DM_THERMAL
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config TARGET_MX6UL_9X9_EVK
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bool "mx6ul_9x9_evk"
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select MX6UL
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select CPU_V7
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select DM
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select DM_THERMAL
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select SUPPORT_SPL
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config TARGET_MX6UL_14X14_EVK
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bool "mx6ul_14x14_evk"
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select MX6UL
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@ -1,4 +1,4 @@
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if TARGET_MX6UL_14X14_EVK
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if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK
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config SYS_BOARD
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default "mx6ul_14x14_evk"
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@ -23,6 +23,9 @@
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#include <linux/sizes.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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@ -210,11 +213,56 @@ struct i2c_pads_info i2c_pad_info1 = {
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.gp = IMX_GPIO_NR(1, 29),
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},
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};
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#ifdef CONFIG_POWER
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#define I2C_PMIC 0
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int power_init_board(void)
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{
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if (is_mx6ul_9x9_evk()) {
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struct pmic *pfuze;
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int ret;
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unsigned int reg, rev_id;
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ret = power_pfuze3000_init(I2C_PMIC);
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if (ret)
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return ret;
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pfuze = pmic_get("PFUZE3000");
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ret = pmic_probe(pfuze);
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if (ret)
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return ret;
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pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
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pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
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reg, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®);
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reg |= 0x1;
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pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
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/* SW1B step ramp up time from 2us to 4us/25mV */
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reg = 0x40;
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pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
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/* SW1B mode to APS/PFM */
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reg = 0xc;
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pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
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/* SW1B standby voltage set to 0.975V */
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reg = 0xb;
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pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
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}
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return 0;
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}
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#endif
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#endif
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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@ -614,6 +662,15 @@ int board_late_init(void)
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add_board_boot_modes(board_boot_modes);
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#endif
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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setenv("board_name", "EVK");
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if (is_mx6ul_9x9_evk())
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setenv("board_rev", "9X9");
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else
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setenv("board_rev", "14X14");
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#endif
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return 0;
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}
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@ -624,7 +681,10 @@ u32 get_board_rev(void)
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int checkboard(void)
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{
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puts("Board: MX6UL 14x14 EVK\n");
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if (is_mx6ul_9x9_evk())
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puts("Board: MX6UL 9x9 EVK\n");
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else
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puts("Board: MX6UL 14x14 EVK\n");
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return 0;
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}
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@ -634,7 +694,76 @@ int checkboard(void)
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
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.grp_ddr_type = 0x00080000,
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#else
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.grp_ddr_type = 0x000c0000,
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#endif
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};
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#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_odt0 = 0x00000000,
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.dram_odt1 = 0x00000000,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000030,
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.dram_sdqs0 = 0x00003030,
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.dram_sdqs1 = 0x00003030,
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.dram_reset = 0x00000030,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpdgctrl0 = 0x20000000,
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.p0_mprddlctl = 0x4040484f,
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.p0_mpwrdlctl = 0x40405247,
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.mpzqlp2ctl = 0x1b4700c7,
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};
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static struct mx6_lpddr2_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 2,
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.width = 16,
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.banks = 4,
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.rowaddr = 14,
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.coladdr = 10,
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.trcd_lp = 1500,
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.trppb_lp = 1500,
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.trpab_lp = 2000,
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.trasmin = 4250,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 18,
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.ncs = 1,
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.cs1_mirror = 0,
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.walat = 0,
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.ralat = 5,
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.mif3_mode = 3,
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.bi_on = 1,
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.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
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.rtt_nom = 0,
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.sde_to_rst = 0, /* LPDDR2 does not need this field */
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.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
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.ddr_type = DDR_TYPE_LPDDR2,
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};
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#else
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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@ -648,24 +777,29 @@ const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_reset = 0x00000030,
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};
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const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00070007,
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.p0_mpdgctrl0 = 0x41490145,
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.p0_mprddlctl = 0x40404546,
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.p0_mpwrdlctl = 0x4040524D,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 4,
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@ -678,6 +812,7 @@ static struct mx6_ddr3_cfg mem_ddr = {
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.trcmin = 4875,
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.trasmin = 3500,
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};
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#endif
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static void ccgr_init(void)
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{
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@ -695,24 +830,8 @@ static void ccgr_init(void)
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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};
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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@ -0,0 +1,8 @@
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_TARGET_MX6UL_9X9_EVK=y
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CONFIG_SPL=y
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CONFIG_CMD_NET=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_DHCP=y
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@ -14,12 +14,16 @@
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#include "mx6_common.h"
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#include <asm/imx-common/gpio.h>
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#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
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/* SPL options */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#include "imx6_spl.h"
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define CONFIG_ROM_UNIFIED_SECTIONS
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_CPUINFO
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@ -61,9 +65,13 @@
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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#define PHYS_SDRAM_SIZE SZ_512M
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/* PMIC only for 9X9 EVK */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE3000
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#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
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#endif
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#undef CONFIG_CMD_IMLS
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@ -75,7 +83,7 @@
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"console=ttymxc0\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_file=imx6ul-14x14-evk.dtb\0" \
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"fdt_file=undefined\0" \
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"fdt_addr=0x83000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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@ -129,9 +137,19 @@
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0"
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"fi;\0" \
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"findfdt="\
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"if test $fdt_file = undefined; then " \
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"if test $board_name = EVK && test $board_rev = 9X9; then " \
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"setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \
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"if test $board_name = EVK && test $board_rev = 14X14; then " \
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"setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
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"if test $fdt_file = undefined; then " \
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"echo WARNING: Could not determine dtb to use; fi; " \
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"fi;\0" \
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#define CONFIG_BOOTCOMMAND \
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"run findfdt;" \
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"mmc dev ${mmcdev};" \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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