Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
utp
Ian Campbell
Tom Rini
parent
ef0f2f5752
commit
da9971d1b3
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@ -119,20 +119,11 @@ void s_init(void)
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#ifdef CONFIG_SPL_BUILD
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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*
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* Unfortunately we can't check how SPL was loaded so assume it's
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* always the first SD/MMC controller, unless it was explicitly
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* stated that SPL is on nand flash.
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* Unfortunately we can't check how SPL was loaded so assume
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* it's always the first SD/MMC controller
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*/
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u32 spl_boot_device(void)
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{
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#if defined(CONFIG_SPL_NAND_SUPPORT)
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/*
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* This is compile time configuration informing SPL, that it
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* was loaded from nand flash.
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*/
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return BOOT_DEVICE_NAND;
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#else
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/*
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* When booting from the SD card, the "eGON.BT0" signature is expected
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* to be found in memory at the address 0x0004 (see the "mksunxiboot"
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@ -153,7 +144,6 @@ u32 spl_boot_device(void)
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return BOOT_DEVICE_MMC1;
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else
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return BOOT_DEVICE_BOARD;
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#endif
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}
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/* No confirmation data available in SPL yet. Hardcode bootmode */
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@ -157,8 +157,6 @@ enum sunxi_gpio_number {
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#define SUN5I_GPB_UART0 2
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#define SUN8I_GPB_UART2 2
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#define SUNXI_GPC_NAND 2
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#define SUNXI_GPC_SDC2 3
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#define SUN6I_GPC_SDC3 4
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@ -1,67 +0,0 @@
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/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_NAND_H
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#define _SUNXI_NAND_H
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#include <linux/types.h>
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struct sunxi_nand
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{
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u32 ctl; /* 0x000 Configure and control */
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u32 st; /* 0x004 Status information */
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u32 intr; /* 0x008 Interrupt control */
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u32 timing_ctl; /* 0x00C Timing control */
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u32 timing_cfg; /* 0x010 Timing configure */
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u32 addr_low; /* 0x014 Low word address */
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u32 addr_high; /* 0x018 High word address */
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u32 block_num; /* 0x01C Data block number */
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u32 data_cnt; /* 0x020 Data counter for transfer */
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u32 cmd; /* 0x024 NDFC commands */
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u32 rcmd_set; /* 0x028 Read command set for vendor NAND mem */
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u32 wcmd_set; /* 0x02C Write command set */
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u32 io_data; /* 0x030 IO data */
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u32 ecc_ctl; /* 0x034 ECC configure and control */
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u32 ecc_st; /* 0x038 ECC status and operation info */
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u32 efr; /* 0x03C Enhanced feature */
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u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */
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u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */
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u32 user_data[16]; /* 0x050[16] User data field */
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u32 efnand_st; /* 0x090 EFNAND status */
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u32 res0[3];
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u32 spare_area; /* 0x0A0 Spare area configure */
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u32 pat_id; /* 0x0A4 Pattern ID register */
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u32 rdata_sta_ctl; /* 0x0A8 Read data status control */
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u32 rdata_sta_0; /* 0x0AC Read data status 0 */
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u32 rdata_sta_1; /* 0x0B0 Read data status 1 */
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u32 res1[3];
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u32 mdma_addr; /* 0x0C0 MBUS DMA Address */
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u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */
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};
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#define SUNXI_NAND_CTL_EN (1 << 0)
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#define SUNXI_NAND_CTL_RST (1 << 1)
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#define SUNXI_NAND_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
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#define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 << 14)
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#define SUNXI_NAND_ST_CMD_INT (1 << 1)
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#define SUNXI_NAND_ST_DMA_INT (1 << 2)
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#define SUNXI_NAND_ST_FIFO_FULL (1 << 3)
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#define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) << 16);
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#define SUNXI_NAND_CMD_SEND_CMD1 (1 << 22)
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#define SUNXI_NAND_CMD_WAIT_FLAG (1 << 23)
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#define SUNXI_NAND_CMD_ORDER_INTERLEAVE 0
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#define SUNXI_NAND_CMD_ORDER_SEQ (1 << 25)
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#define SUNXI_NAND_ECC_CTL_ECC_EN (1 << 0)
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#define SUNXI_NAND_ECC_CTL_PIPELINE (1 << 3)
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#define SUNXI_NAND_ECC_CTL_BS_512B (1 << 5)
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#define SUNXI_NAND_ECC_CTL_RND_EN (1 << 9)
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#define SUNXI_NAND_ECC_CTL_MODE(a) ((a) << 12)
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#define SUNXI_NAND_ECC_CTL_RND_SEED(a) ((a) << 16)
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#endif /* _SUNXI_NAND_H */
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@ -280,18 +280,6 @@ config MMC_SUNXI_SLOT_EXTRA
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slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
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support for this.
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config SPL_NAND_SUPPORT
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bool "SPL/NAND mode support"
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depends on SPL
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default n
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---help---
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This enables support for booting from NAND internal
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memory. U-Boot SPL doesn't detect where is it load from,
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therefore this option is needed to properly load image from
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flash. Option also disables MMC functionality on U-Boot due to
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initialization errors encountered, when both controllers are
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enabled.
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config USB0_VBUS_PIN
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string "Vbus enable pin for usb0 (otg)"
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default ""
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@ -22,9 +22,6 @@
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#ifdef CONFIG_AXP221_POWER
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#include <axp221.h>
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#endif
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#ifdef CONFIG_NAND_SUNXI
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#include <nand.h>
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#endif
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/display.h>
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@ -318,21 +315,6 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_NAND
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void board_nand_init(void)
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{
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unsigned int pin;
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static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS;
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/* Configure AHB muxes to connect output pins with NAND controller */
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for (pin = 0; pin < 16; pin++)
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sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND);
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for (pin = 0; pin < ARRAY_SIZE(ports); pin++)
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sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND);
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}
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#endif
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void i2c_init_board(void)
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{
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#ifdef CONFIG_I2C0_ENABLE
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@ -73,6 +73,5 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
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obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
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obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
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obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
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obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
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endif # drivers
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@ -1,273 +0,0 @@
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/*
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* Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
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* Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
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* Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* \todo Detect chip parameters (page size, ECC mode, randomisation...)
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/nand.h>
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void
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nand_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
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u32 val;
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board_nand_init();
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/* "un-gate" NAND clock and clock source
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* This assumes that the clock was already correctly configured by
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* BootROM */
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
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#ifdef CONFIG_MACH_SUN9I
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setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
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#else
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
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#endif
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setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
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val = readl(&nand->ctl);
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val |= SUNXI_NAND_CTL_RST;
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writel(val, &nand->ctl);
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/* Wait until reset pin is deasserted */
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do {
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val = readl(&nand->ctl);
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if (!(val & SUNXI_NAND_CTL_RST))
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break;
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} while (1);
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/** \todo Chip select, currently kind of static */
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val = readl(&nand->ctl);
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val &= 0xf0fff0f2;
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val |= SUNXI_NAND_CTL_EN;
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val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
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writel(val, &nand->ctl);
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writel(0x100, &nand->timing_ctl);
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writel(0x7ff, &nand->timing_cfg);
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/* reset CMD */
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val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG |
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NAND_CMD_RESET;
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writel(val, &nand->cmd);
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do {
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val = readl(&nand->st);
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if (val & (1<<1))
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break;
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udelay(1000);
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} while (1);
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printf("Nand initialised\n");
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}
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int
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nand_wait_timeout(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000; /* 1s */
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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return -ETIMEDOUT;
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}
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return 0;
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}
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/* random seed */
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static const uint16_t random_seed[128] = {
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0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
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0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
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0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
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0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
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0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
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0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
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0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
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0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
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0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
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0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
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0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
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0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
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0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
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0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
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0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
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0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
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};
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uint32_t ecc_errors = 0;
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static void
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nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
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{
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static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
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int i;
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uint32_t ecc_mode;
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u32 ecc;
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u16 seed = 0;
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for (i = 0; i < ARRAY_SIZE(strength); i++) {
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if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
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ecc_mode = i;
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break;
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}
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}
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if (i == ARRAY_SIZE(strength)) {
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printf("ECC strength unsupported\n");
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return;
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}
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ecc = SUNXI_NAND_ECC_CTL_ECC_EN |
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SUNXI_NAND_ECC_CTL_PIPELINE |
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SUNXI_NAND_ECC_CTL_RND_EN |
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SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
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if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
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ecc |= SUNXI_NAND_ECC_CTL_BS_512B;
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if (syndrome)
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seed = 0x4A80;
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else
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seed = random_seed[page % ARRAY_SIZE(random_seed)];
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ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
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writel(ecc, &nand->ecc_ctl);
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}
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/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
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void
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nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
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int syndrome)
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{
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struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
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struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
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uint32_t shift;
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uint32_t page;
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uint32_t addr;
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uint32_t oob_offset;
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uint32_t ecc_bytes;
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u32 val;
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u32 cmd;
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page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
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if (page > 0xFFFF) {
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/* TODO: currently this is not supported */
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printf("Reading from address >= %08X is not allowed.\n",
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0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
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return;
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}
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shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
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writel(0, &nand->ecc_st);
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/* ECC_CTL, randomization */
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ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
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fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
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ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
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ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
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ecc_bytes += 4;
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nand_config_ecc(nand, page, syndrome);
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if (syndrome) {
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/* shift every 1kB in syndrome */
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shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
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oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
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} else {
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oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
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(shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
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}
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addr = (page << 16) | shift;
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/* DMA */
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val = readl(&nand->ctl);
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writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
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writel(oob_offset, &nand->spare_area);
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/* DMAC
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* \todo Separate this into a tidy driver */
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writel(0x0, &dma->irq_en); /* clear dma interrupts */
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writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
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writel(dst , &dma_cfg->dst_addr);
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writel(0x00007F0F , &dma_cfg->ddma_para);
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writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
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val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) |
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SUNXI_DMA_CTL_MODE_IO |
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SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 |
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SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) |
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SUNXI_DMA_CTL_DST_DATA_WIDTH_32 |
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SUNXI_DMA_CTL_TRIGGER;
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writel(val, &dma_cfg->ctl);
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writel(0x00E00530, &nand->rcmd_set);
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nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
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||||
writel(1 , &nand->block_num);
|
||||
writel(addr, &nand->addr_low);
|
||||
writel(0 , &nand->addr_high);
|
||||
|
||||
/* CMD (PAGE READ) */
|
||||
cmd = 0x85E80000;
|
||||
cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
|
||||
cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
|
||||
SUNXI_NAND_CMD_ORDER_INTERLEAVE);
|
||||
writel(cmd, &nand->cmd);
|
||||
|
||||
if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
|
||||
SUNXI_NAND_ST_DMA_INT)) {
|
||||
printf("NAND timeout reading data\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
|
||||
printf("NAND timeout reading data\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (readl(&nand->ecc_st))
|
||||
ecc_errors++;
|
||||
}
|
||||
|
||||
int
|
||||
nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
|
||||
{
|
||||
struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
|
||||
dma_addr_t dst_block;
|
||||
dma_addr_t dst_end;
|
||||
phys_addr_t addr = offs;
|
||||
|
||||
dst_end = ((dma_addr_t) dest) + size;
|
||||
|
||||
memset((void *)dest, 0x0, size);
|
||||
ecc_errors = 0;
|
||||
for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
|
||||
dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
|
||||
addr += CONFIG_NAND_SUNXI_ECC_STEP) {
|
||||
/* syndrome read first 4MiB to match Allwinner BootROM */
|
||||
nand_read_block(nand, addr, dst_block, addr < 0x400000);
|
||||
}
|
||||
|
||||
if (ecc_errors)
|
||||
printf("Error: %d ECC failures detected\n", ecc_errors);
|
||||
return ecc_errors == 0;
|
||||
}
|
||||
|
||||
void
|
||||
nand_deselect(void)
|
||||
{}
|
||||
|
|
@ -18,7 +18,6 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_SUNXI_USB_PHYS 3
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24}
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
|
|
|
|||
|
|
@ -19,9 +19,6 @@
|
|||
|
||||
#define CONFIG_SUNXI_USB_PHYS 2
|
||||
|
||||
/* \todo A13 only defines port 19, whereas A10s requires each of these */
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19}
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -27,8 +27,6 @@
|
|||
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {24, 25, 26}
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -24,8 +24,6 @@
|
|||
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18, 19, 20, 21, 22, 24}
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -23,10 +23,8 @@
|
|||
#define CONFIG_ARMV7_PSCI 1
|
||||
#if defined(CONFIG_MACH_SUN8I_A23)
|
||||
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {16, 17, 18}
|
||||
#elif defined(CONFIG_MACH_SUN8I_A33)
|
||||
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
|
||||
#define CONFIG_NAND_SUNXI_GPC_PORTS {16}
|
||||
#else
|
||||
#error Unsupported sun8i variant
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -146,10 +146,8 @@
|
|||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_MMC_SUNXI
|
||||
#define CONFIG_MMC_SUNXI_SLOT 0
|
||||
#if !defined(CONFIG_SPL_NAND_SUPPORT)
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
|
||||
#endif /* CONFIG_SPL_NAND_SUPPORT */
|
||||
#endif
|
||||
|
||||
/* 4MB of malloc() pool */
|
||||
|
|
@ -351,24 +349,6 @@ extern int soft_i2c_gpio_scl;
|
|||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_NAND
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_NAND_SUNXI
|
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x000400
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x008000
|
||||
|
||||
/* \todo Make these parameterisable in kernel config ? */
|
||||
#define CONFIG_NAND_SUNXI_PAGE_SIZE 8192
|
||||
#define CONFIG_NAND_SUNXI_ECC_STEP 1024
|
||||
#define CONFIG_NAND_SUNXI_ECC_STRENGTH 40
|
||||
#define CONFIG_NAND_SUNXI_ADDR_CYCLES 5
|
||||
|
||||
#ifndef CONFIG_NAND_SUNXI_GPC_PORTS
|
||||
#error "No NAND GPC ports defined, NAND unsupported"
|
||||
#endif
|
||||
#endif /* CONFIG_SPL_NAND_SUPPORT */
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue