cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
stroese
parent
75b1fa7864
commit
de8d5a3600
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2002
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* (C) Copyright 2002-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -24,49 +24,41 @@
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <pci.h>
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#ifdef CONFIG_SDRAM_BANK0
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#define MAGIC0 0x00000000
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#define MAGIC1 0x11111111
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#define MAGIC2 0x22222222
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#define MAGIC3 0x33333333
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#define MAGIC4 0x44444444
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#define MAGIC5 0x55555555
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#define MAGIC6 0x66666666
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#define ADDR_ZERO 0x00000000
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#define ADDR_400 0x00000400
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#define ADDR_01MB 0x00100000
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#define ADDR_08MB 0x00800000
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#define ADDR_16MB 0x01000000
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#define ADDR_32MB 0x02000000
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#define ADDR_64MB 0x04000000
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#define ADDR_128MB 0x08000000
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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/*-----------------------------------------------------------------------
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*/
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struct sdram_conf_s {
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unsigned long size;
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unsigned long reg;
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};
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typedef struct sdram_conf_s sdram_conf_t;
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sdram_conf_t mb0cf[] = {
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{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
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{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
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{(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
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{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
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{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
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};
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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void sdram_init(void)
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{
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ulong speed;
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ulong sdtr1;
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ulong rtr;
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/*
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* Determine SDRAM speed
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*/
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speed = get_bus_freq(0); /* parameter not used on ppc4xx */
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int i;
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/*
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* Support for 100MHz and 133MHz SDRAM
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*/
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if (speed > 100000000) {
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if (get_bus_freq(0) > 100000000) {
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/*
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* 133 MHz SDRAM
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*/
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@ -80,218 +72,37 @@ void sdram_init(void)
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rtr = 0x05f00000;
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}
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4)
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*/
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mtsdram0(mem_mb0cf, 0x000A4001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/*
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* Wait for 200us
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*/
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 128 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_08MB = MAGIC1;
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*(volatile ulong *)ADDR_16MB = MAGIC2;
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*(volatile ulong *)ADDR_32MB = MAGIC3;
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*(volatile ulong *)ADDR_64MB = MAGIC4;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC1) &&
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(*(volatile ulong *)ADDR_16MB == MAGIC2) &&
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(*(volatile ulong *)ADDR_32MB == MAGIC3)) {
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for (i=0; i<N_MB0CF; i++) {
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/*
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* OK, 128MB detected -> all done
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* Disable memory controller.
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*/
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return;
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}
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Now test for 64 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00084001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/*
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* Wait for 200us
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*/
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 64 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_08MB = MAGIC1;
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*(volatile ulong *)ADDR_16MB = MAGIC2;
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*(volatile ulong *)ADDR_32MB = MAGIC3;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC1) &&
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(*(volatile ulong *)ADDR_16MB == MAGIC2)) {
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/*
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* OK, 64MB detected -> all done
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* Set MB0CF for bank 0.
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*/
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return;
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}
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mtsdram0(mem_mb0cf, mb0cf[i].reg);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/*
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* Now test for 32 MByte...
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*/
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udelay(200);
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00062001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 32 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_400 = MAGIC1;
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*(volatile ulong *)ADDR_08MB = MAGIC2;
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*(volatile ulong *)ADDR_16MB = MAGIC3;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_400 == MAGIC1) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC2)) {
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/*
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* OK, 32MB detected -> all done
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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return;
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mtsdram0(mem_mcopt1, 0x80800000);
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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/*
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* OK, size detected -> all done
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*/
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return;
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}
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}
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/*
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* Now test for 16 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
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*/
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mtsdram0(mem_mb0cf, 0x00046001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 16 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_400 = MAGIC1;
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*(volatile ulong *)ADDR_01MB = MAGIC5;
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*(volatile ulong *)ADDR_08MB = MAGIC2;
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/* *(volatile ulong *)ADDR_16MB = MAGIC3;*/
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_400 == MAGIC1) &&
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(*(volatile ulong *)ADDR_01MB == MAGIC5) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC2)) {
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/*
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* OK, 16MB detected -> all done
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*/
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return;
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}
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/*
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* Setup for 4 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-4MB) Address Mode 5 since 11x8(2)
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*/
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mtsdram0(mem_mb0cf, 0x00008001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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}
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#endif /* CONFIG_SDRAM_BANK0 */
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