MX: RTC13783 uses general function to access PMIC
The RTC is part of the Freescale's PMIC controller. Use general function to access to PMIC internal registers. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
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@ -23,53 +23,30 @@
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#include <common.h>
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#include <rtc.h>
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#include <spi.h>
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static struct spi_slave *slave;
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#include <fsl_pmic.h>
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int rtc_get(struct rtc_time *rtc)
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{
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u32 day1, day2, time;
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u32 reg;
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int err, tim, i = 0;
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if (!slave) {
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/* FIXME: Verify the max SCK rate */
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slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
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CONFIG_MC13783_SPI_CS, 1000000,
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SPI_MODE_2 | SPI_CS_HIGH);
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if (!slave)
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return -1;
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}
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if (spi_claim_bus(slave))
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return -1;
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int tim, i = 0;
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do {
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reg = 0x2c000000;
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err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
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SPI_XFER_BEGIN | SPI_XFER_END);
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day1 = pmic_reg_read(REG_RTC_DAY);
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if (day1 < 0)
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return -1;
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if (err)
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return err;
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time = pmic_reg_read(REG_RTC_TIME);
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if (time < 0)
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return -1;
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reg = 0x28000000;
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err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
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SPI_XFER_BEGIN | SPI_XFER_END);
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day2 = pmic_reg_read(REG_RTC_DAY);
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if (day2 < 0)
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return -1;
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if (err)
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return err;
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reg = 0x2c000000;
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err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
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SPI_XFER_BEGIN | SPI_XFER_END);
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if (err)
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return err;
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} while (day1 != day2 && i++ < 3);
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spi_release_bus(slave);
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tim = day1 * 86400 + time;
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to_tm(tim, rtc);
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rtc->tm_yday = 0;
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@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc)
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int rtc_set(struct rtc_time *rtc)
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{
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u32 time, day, reg;
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if (!slave) {
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/* FIXME: Verify the max SCK rate */
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slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
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CONFIG_MC13783_SPI_CS, 1000000,
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SPI_MODE_2 | SPI_CS_HIGH);
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if (!slave)
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return -1;
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}
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u32 time, day;
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time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
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rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
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day = time / 86400;
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time %= 86400;
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if (spi_claim_bus(slave))
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return -1;
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reg = 0x2c000000 | day | 0x80000000;
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spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
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SPI_XFER_BEGIN | SPI_XFER_END);
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reg = 0x28000000 | time | 0x80000000;
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spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
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SPI_XFER_BEGIN | SPI_XFER_END);
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spi_release_bus(slave);
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pmic_reg_write(REG_RTC_DAY, day);
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pmic_reg_write(REG_RTC_TIME, time);
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return 0;
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}
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@ -68,10 +68,13 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS0 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@ -65,10 +65,12 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS0 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@ -69,12 +69,13 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 2
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS2 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 2
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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