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Document the clocks in DCD

utp
Martin T. H. Sandsmark 2016-08-23 12:12:28 +02:00
parent 5fee53e5d1
commit e0be6171bb
1 changed files with 19 additions and 11 deletions
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30
board/reMarkable/zero-gravitas/imximage.cfg
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@ -27,27 +27,35 @@ BOOT_FROM sd
/* =============================================================================*/
/* Enable all clocks (they are disabled by ROM code*/
/* =============================================================================*/
/* setmem /32 0x020c4068 = 0xffffffff*/
/* setmem /32 0x020c406c = 0xffffffff*/
/* setmem /32 0x020c4070 = 0xffffffff*/
/* setmem /32 0x020c4074 = 0xffffffff*/
/* setmem /32 0x020c4078 = 0xffffffff*/
/* setmem /32 0x020c407c = 0xffffffff*/
/* setmem /32 0x020c4080 = 0xffffffff*/
/* setmem /32 0x020c4084 = 0xffffffff*/
/* CCGR0; CAAM */
DATA 4 0x020c4068 0xffffffff
/* CCGR1; I2C4, SPI, ENET */
DATA 4 0x020c406c 0xffffffff
/* CCGR2; I2C1, I2C2, I2C3, LCDIF, OCOTP, GPMI */
DATA 4 0x020c4070 0xffffffff
/* CCGR3; ENET, LCDIF, QSPI 0, IPU 0 */
DATA 4 0x020c4074 0xffffffff
/* CCGR4; GPMI, PCIE, QSPI 1 */
DATA 4 0x020c4078 0xffffffff
/* CCGR5; UART, SATA */
DATA 4 0x020c407c 0xffffffff
/* CCGR6; USDHC, IPU, USBOH3, CAAM EMI slow clock */
DATA 4 0x020c4080 0xffffffff
/* ????; seems to be in several DCDs as well in the DDR script aid */
/* Might be General Purpose Timer #0 Controller (USB_UOG1_GPTIMER0CTRL) */
/* However, the absolute address is wrong in that case, might be some offset */
DATA 4 0x020c4084 0xffffffff
/* DDR clk to 400MHz*/
/* DDR clk to 400MHz */
/* CCM Bus Clock Multiplexer Register (CCM_CBCMR) in reference manual */
DATA 4 0x020c4018 0x00260324
/* =============================================================================*/