diff --git a/doc/README.x86 b/doc/README.x86
index 41acf0bb92..889373efbf 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -864,6 +864,15 @@ PCIe root port's configuration registers will cause system hang while it is
 held in reset. For more details, check how they are implemented by the Intel
 Galileo board support codes in board/intel/galileo/galileo.c.
 
+coreboot:
+
+See scripts/coreboot.sed which can assist with porting coreboot code into
+U-Boot drivers. It will not resolve all build errors, but will perform common
+transformations. Remember to add attribution to coreboot for new files added
+to U-Boot. This should go at the top of each file and list the coreboot
+filename where the code originated.
+
+
 TODO List
 ---------
 - Audio
diff --git a/scripts/coreboot.sed b/scripts/coreboot.sed
new file mode 100644
index 0000000000..42e1f3aea7
--- /dev/null
+++ b/scripts/coreboot.sed
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Script to convert coreboot code to something similar to what U-Boot uses
+# sed -f coreboot.sed <coreboot_file.c>
+# Remember to add attribution to coreboot for new files added to U-Boot.
+s/REG_RES_WRITE32(\(.*\), \(.*\), \(.*\)),/writel(\3, base + \2);/
+s/REG_RES_POLL32(\(.*\), \(.*\), \(.*\), \(.*\), \(.*\)),/ret = poll32(base + \2, \3, \4, \5);/
+s/REG_RES_OR32(\(.*\), \(.*\), \(.*\)),/setbits_le32(base + \2, \3);/
+s/REG_RES_RMW32(\(.*\), \(.*\), \(.*\), \(.*\)),/clrsetbits_le32(base + \2, ~\3, \4);/
+/REG_SCRIPT_END/d
+s/read32/readl/
+s/write32(\(.*\), \(.*\))/writel(\2, \1)/
+s/conf->/plat->/
+s/static const struct reg_script \(.*\)_script\[\] = {/static int \1(struct udevice *dev)/