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armv7: rename cache related CONFIG flags 

Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF

Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
 * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message
utp
Aneesh V 2011-06-16 23:30:48 +00:00 committed by Albert ARIBAUD
parent 2c451f7831
commit e47f2db537
36 changed files with 42 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/cpu/arm1136/start.S
View File

@ -512,10 +512,10 @@ fiq:
.align 5
.global arm1136_cache_flush
arm1136_cache_flush:
#if !defined(CONFIG_SYS_NO_ICACHE)
#if !defined(CONFIG_SYS_ICACHE_OFF)
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
#endif
#if !defined(CONFIG_SYS_NO_DCACHE)
#if !defined(CONFIG_SYS_DCACHE_OFF)
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
#endif
mov pc, lr @ back to caller

3
arch/arm/cpu/armv7/cpu.c
View File

@ -35,9 +35,6 @@
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
#ifndef CONFIG_L2_OFF
#include <asm/arch/sys_proto.h>
#endif
static void cache_flush(void);

2
arch/arm/include/asm/global_data.h
View File

@ -70,7 +70,7 @@ typedef struct global_data {
unsigned long irq_sp; /* irq stack pointer */
unsigned long start_addr_sp; /* start_addr_stackpointer */
unsigned long reloc_off;
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
#endif
void **jt; /* jump table */

2
arch/arm/lib/Makefile
View File

@ -39,9 +39,7 @@ GLCOBJS += div0.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cache.o
ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y += cache-cp15.o
endif
COBJS-y += interrupts.o
COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o

2
arch/arm/lib/board.c
View File

@ -326,7 +326,7 @@ void board_init_f (ulong bootflag)
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
addr -= (4096 * 4);

6
arch/arm/lib/cache-cp15.c
View File

@ -24,7 +24,7 @@
#include <common.h>
#include <asm/system.h>
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
#define CACHE_SETUP 0x1a
@ -118,7 +118,7 @@ static void cache_disable(uint32_t cache_bit)
}
#endif
#ifdef CONFIG_SYS_NO_ICACHE
#ifdef CONFIG_SYS_ICACHE_OFF
void icache_enable (void)
{
return;
@ -150,7 +150,7 @@ int icache_status(void)
}
#endif
#ifdef CONFIG_SYS_NO_DCACHE
#ifdef CONFIG_SYS_DCACHE_OFF
void dcache_enable (void)
{
return;

8
board/armltd/integrator/split_by_variant.sh
View File

@ -103,16 +103,16 @@ case "$cpu" in
#undef CONFIG_CM_INIT /* CM may not have initialization reg */
#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
/* May not be processor without cache support */
#define CONFIG_SYS_NO_ICACHE 1
#define CONFIG_SYS_NO_DCACHE 1
#define CONFIG_SYS_ICACHE_OFF 1
#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
arm720t)
cat >> ${config_file} << _EOF
/* May not be processor without cache support */
#define CONFIG_SYS_NO_ICACHE 1
#define CONFIG_SYS_NO_DCACHE 1
#define CONFIG_SYS_ICACHE_OFF 1
#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
esac

2
common/cmd_bdinfo.c
View File

@ -345,7 +345,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
#endif
printf("baudrate = %d bps\n", bd->bi_baudrate);
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);

3
include/configs/B2.h
View File

@ -38,7 +38,8 @@
#define CONFIG_B2 1 /* on an B2 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#define CONFIG_SYS_NO_CP15_CACHE
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/

2
include/configs/assabet.h
View File

@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1

2
include/configs/ca9x4_ct_vxp.h
View File

@ -41,7 +41,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_OF_LIBFDT 1

2
include/configs/cerf250.h
View File

@ -43,7 +43,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/cradle.h
View File

@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Size of malloc() pool

2
include/configs/csb226.h
View File

@ -44,7 +44,7 @@
/* for timer/console/ethernet */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Hardware drivers

2
include/configs/dnp1110.h
View File

@ -42,7 +42,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/efikamx.h
View File

@ -38,7 +38,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
/*
* Bootloader Components Configuration

3
include/configs/evb4510.h
View File

@ -43,7 +43,8 @@
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */
#define CONFIG_EVB4510 1 /* on an EVB4510 Board */
#define CONFIG_SYS_NO_CP15_CACHE
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024)

2
include/configs/gcplus.h
View File

@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1

2
include/configs/innokom.h
View File

@ -43,7 +43,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Hardware drivers

2
include/configs/jornada.h
View File

@ -32,7 +32,7 @@
#define CONFIG_SYS_TEXT_BASE 0xC1F00000
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
/* Console setting */

2
include/configs/lart.h
View File

@ -36,7 +36,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/lubbock.h
View File

@ -47,7 +47,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/mx51evk.h
View File

@ -35,7 +35,7 @@
#define CONFIG_SYS_TEXT_BASE 0x97800000
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>
/*

2
include/configs/mx53evk.h
View File

@ -29,7 +29,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>

2
include/configs/omap4_panda.h
View File

@ -46,7 +46,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */

2
include/configs/omap4_sdp4430.h
View File

@ -47,7 +47,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */

2
include/configs/pleb2.h
View File

@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/pxa255_idp.h
View File

@ -69,7 +69,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/s5pc210_universal.h
View File

@ -43,7 +43,7 @@
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x44800000

2
include/configs/shannon.h
View File

@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool

2
include/configs/tegra2-common.h
View File

@ -31,7 +31,7 @@
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
#define CONFIG_L2_OFF /* No L2 cache */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */

2
include/configs/trizepsiv.h
View File

@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
#define RTC

2
include/configs/vision2.h
View File

@ -26,7 +26,7 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
#define CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>

2
include/configs/xaeniax.h
View File

@ -51,7 +51,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* select serial console configuration

2
include/configs/xm250.h
View File

@ -38,7 +38,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool; this lives below the uppermost 128 KiB which are

2
include/configs/zylonite.h
View File

@ -48,7 +48,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool