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@ -10,10 +10,10 @@
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* SPDX-License-Identifier: GPL-2.0
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*/
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#define DEBUG
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#define pr_fmt(fmt) "tegra-pcie: " fmt
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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@ -177,7 +177,12 @@ DECLARE_GLOBAL_DATA_PTR;
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#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
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#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
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struct tegra_pcie;
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enum tegra_pci_id {
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TEGRA20_PCIE,
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TEGRA30_PCIE,
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TEGRA124_PCIE,
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TEGRA210_PCIE,
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};
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struct tegra_pcie_port {
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struct tegra_pcie *pcie;
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@ -207,10 +212,6 @@ struct tegra_pcie {
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struct fdt_resource afi;
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struct fdt_resource cs;
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struct fdt_resource prefetch;
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struct fdt_resource mem;
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struct fdt_resource io;
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struct list_head ports;
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unsigned long xbar;
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@ -218,11 +219,6 @@ struct tegra_pcie {
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struct tegra_xusb_phy *phy;
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};
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static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose)
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{
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return container_of(hose, struct tegra_pcie, hose);
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}
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static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
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unsigned long offset)
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{
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@ -284,46 +280,54 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
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return 0;
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}
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return -1;
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return -EFAULT;
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}
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static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf,
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int where, u32 *value)
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static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct tegra_pcie *pcie = to_tegra_pcie(hose);
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unsigned long address;
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struct tegra_pcie *pcie = dev_get_priv(bus);
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unsigned long address, value;
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int err;
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err = tegra_pcie_conf_address(pcie, bdf, where, &address);
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err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
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if (err < 0) {
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*value = 0xffffffff;
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return 1;
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value = 0xffffffff;
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goto done;
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}
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*value = readl(address);
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value = readl(address);
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/* fixup root port class */
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if (PCI_BUS(bdf) == 0) {
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if (where == PCI_CLASS_REVISION) {
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*value &= ~0x00ff0000;
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*value |= PCI_CLASS_BRIDGE_PCI << 16;
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if (offset == PCI_CLASS_REVISION) {
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value &= ~0x00ff0000;
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value |= PCI_CLASS_BRIDGE_PCI << 16;
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}
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}
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done:
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*valuep = pci_conv_32_to_size(value, offset, size);
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return 0;
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}
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static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf,
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int where, u32 value)
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static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct tegra_pcie *pcie = to_tegra_pcie(hose);
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struct tegra_pcie *pcie = dev_get_priv(bus);
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unsigned long address;
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ulong old;
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int err;
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err = tegra_pcie_conf_address(pcie, bdf, where, &address);
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err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
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if (err < 0)
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return 1;
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return 0;
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old = readl(address);
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value = pci_conv_size_to_32(old, value, offset, size);
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writel(value, address);
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return 0;
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@ -348,12 +352,10 @@ static int tegra_pcie_port_parse_dt(const void *fdt, int node,
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}
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static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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unsigned long *xbar)
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enum tegra_pci_id id, unsigned long *xbar)
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{
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enum fdt_compat_id id = fdtdec_lookup(fdt, node);
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switch (id) {
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case COMPAT_NVIDIA_TEGRA20_PCIE:
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case TEGRA20_PCIE:
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switch (lanes) {
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case 0x00000004:
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debug("single-mode configuration\n");
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@ -366,8 +368,7 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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return 0;
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}
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break;
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case COMPAT_NVIDIA_TEGRA30_PCIE:
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case TEGRA30_PCIE:
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switch (lanes) {
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case 0x00000204:
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debug("4x1, 2x1 configuration\n");
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@ -385,9 +386,8 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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return 0;
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}
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break;
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case COMPAT_NVIDIA_TEGRA124_PCIE:
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case COMPAT_NVIDIA_TEGRA210_PCIE:
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case TEGRA124_PCIE:
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case TEGRA210_PCIE:
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switch (lanes) {
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case 0x0000104:
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debug("4x1, 1x1 configuration\n");
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@ -400,7 +400,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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return 0;
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}
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break;
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default:
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break;
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}
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@ -408,84 +407,6 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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return -FDT_ERR_NOTFOUND;
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}
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static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
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struct tegra_pcie *pcie)
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{
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int parent, na_parent, na_pcie, ns_pcie;
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const u32 *ptr, *end;
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int len;
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parent = fdt_parent_offset(fdt, node);
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if (parent < 0) {
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error("Can't find PCI parent node\n");
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return -FDT_ERR_NOTFOUND;
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}
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na_parent = fdt_address_cells(fdt, parent);
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if (na_parent < 1) {
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error("bad #address-cells for PCIE parent\n");
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return -FDT_ERR_NOTFOUND;
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}
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na_pcie = fdt_address_cells(fdt, node);
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if (na_pcie < 1) {
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error("bad #address-cells for PCIE\n");
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return -FDT_ERR_NOTFOUND;
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}
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ns_pcie = fdt_size_cells(fdt, node);
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if (ns_pcie < 1) {
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error("bad #size-cells for PCIE\n");
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return -FDT_ERR_NOTFOUND;
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}
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ptr = fdt_getprop(fdt, node, "ranges", &len);
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if (!ptr) {
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error("missing \"ranges\" property");
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return -FDT_ERR_NOTFOUND;
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}
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end = ptr + len / 4;
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while (ptr < end) {
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struct fdt_resource *res = NULL;
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u32 space = fdt32_to_cpu(*ptr);
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switch ((space >> 24) & 0x3) {
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case 0x01:
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res = &pcie->io;
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break;
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case 0x02: /* 32 bit */
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case 0x03: /* 64 bit */
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if (space & (1 << 30))
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res = &pcie->prefetch;
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else
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res = &pcie->mem;
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break;
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}
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if (res) {
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int start_low = na_pcie + (na_parent - 1);
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int size_low = na_pcie + na_parent + (ns_pcie - 1);
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res->start = fdt32_to_cpu(ptr[start_low]);
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res->end = res->start + fdt32_to_cpu(ptr[size_low]);
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}
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ptr += na_pcie + na_parent + ns_pcie;
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}
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debug("PCI regions:\n");
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debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
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debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
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&pcie->mem.end);
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debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
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&pcie->prefetch.end);
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return 0;
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}
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static int tegra_pcie_parse_port_info(const void *fdt, int node,
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unsigned int *index,
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unsigned int *lanes)
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@ -512,7 +433,12 @@ static int tegra_pcie_parse_port_info(const void *fdt, int node,
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return 0;
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}
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static int tegra_pcie_parse_dt(const void *fdt, int node,
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int __weak tegra_pcie_board_init(void)
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{
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return 0;
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}
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static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
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struct tegra_pcie *pcie)
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{
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int err, subnode;
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@ -539,6 +465,8 @@ static int tegra_pcie_parse_dt(const void *fdt, int node,
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return err;
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}
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tegra_pcie_board_init();
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pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
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if (pcie->phy) {
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err = tegra_xusb_phy_prepare(pcie->phy);
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@ -548,12 +476,6 @@ static int tegra_pcie_parse_dt(const void *fdt, int node,
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}
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}
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err = tegra_pcie_parse_dt_ranges(fdt, node, pcie);
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if (err < 0) {
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error("failed to parse \"ranges\" property");
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return err;
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}
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fdt_for_each_subnode(fdt, subnode, node) {
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unsigned int index = 0, num_lanes = 0;
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struct tegra_pcie_port *port;
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@ -588,7 +510,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node,
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port->pcie = pcie;
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}
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err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar);
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err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
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if (err < 0) {
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error("invalid lane configuration");
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return err;
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@ -597,11 +519,6 @@ static int tegra_pcie_parse_dt(const void *fdt, int node,
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return 0;
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}
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int __weak tegra_pcie_board_init(void)
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{
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return 0;
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}
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static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc *soc = pcie->soc;
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@ -788,9 +705,12 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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return 0;
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}
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static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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static int tegra_pcie_setup_translations(struct udevice *bus)
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{
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struct tegra_pcie *pcie = dev_get_priv(bus);
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unsigned long fpci, axi, size;
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struct pci_region *io, *mem, *pref;
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int count;
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/* BAR 0: type 1 extended configuration space */
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fpci = 0xfe100000;
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@ -801,28 +721,32 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
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afi_writel(pcie, fpci, AFI_FPCI_BAR0);
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count = pci_get_regions(bus, &io, &mem, &pref);
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if (count != 3)
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return -EINVAL;
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/* BAR 1: downstream I/O */
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fpci = 0xfdfc0000;
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size = fdt_resource_size(&pcie->io);
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axi = pcie->io.start;
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size = io->size;
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axi = io->phys_start;
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afi_writel(pcie, axi, AFI_AXI_BAR1_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
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afi_writel(pcie, fpci, AFI_FPCI_BAR1);
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/* BAR 2: prefetchable memory */
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fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = fdt_resource_size(&pcie->prefetch);
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axi = pcie->prefetch.start;
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fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = pref->size;
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axi = pref->phys_start;
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afi_writel(pcie, axi, AFI_AXI_BAR2_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
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afi_writel(pcie, fpci, AFI_FPCI_BAR2);
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/* BAR 3: non-prefetchable memory */
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fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = fdt_resource_size(&pcie->mem);
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axi = pcie->mem.start;
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fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
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size = mem->size;
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axi = mem->phys_start;
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afi_writel(pcie, axi, AFI_AXI_BAR3_START);
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afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
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@ -848,6 +772,8 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
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afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
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afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
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return 0;
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}
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static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
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@ -1001,209 +927,116 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie)
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return 0;
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}
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static const struct tegra_pcie_soc tegra20_pcie_soc = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
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.has_pex_clkreq_en = false,
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.has_pex_bias_ctrl = false,
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.has_cml_clk = false,
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.has_gen2 = false,
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.force_pca_enable = false,
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static const struct tegra_pcie_soc pci_tegra_soc[] = {
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[TEGRA20_PCIE] = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
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.has_pex_clkreq_en = false,
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.has_pex_bias_ctrl = false,
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.has_cml_clk = false,
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.has_gen2 = false,
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},
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[TEGRA30_PCIE] = {
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.num_ports = 3,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = false,
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},
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[TEGRA124_PCIE] = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = true,
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},
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[TEGRA210_PCIE] = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = true,
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.force_pca_enable = true,
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}
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};
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static const struct tegra_pcie_soc tegra30_pcie_soc = {
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.num_ports = 3,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = false,
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.force_pca_enable = false,
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};
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static const struct tegra_pcie_soc tegra124_pcie_soc = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = true,
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.force_pca_enable = false,
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};
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static const struct tegra_pcie_soc tegra210_pcie_soc = {
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.num_ports = 2,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = true,
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.force_pca_enable = true,
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};
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static int process_nodes(const void *fdt, int nodes[], unsigned int count)
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static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
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{
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unsigned int i;
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uint64_t dram_end;
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uint32_t pci_dram_size;
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struct tegra_pcie *pcie = dev_get_priv(dev);
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enum tegra_pci_id id;
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/* Clip PCI-accessible DRAM to 32-bits */
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dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size;
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if (dram_end > 0x100000000)
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dram_end = 0x100000000;
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pci_dram_size = dram_end - NV_PA_SDRAM_BASE;
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id = dev_get_driver_data(dev);
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pcie->soc = &pci_tegra_soc[id];
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for (i = 0; i < count; i++) {
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const struct tegra_pcie_soc *soc;
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struct tegra_pcie *pcie;
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enum fdt_compat_id id;
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int err;
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INIT_LIST_HEAD(&pcie->ports);
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if (!fdtdec_get_is_enabled(fdt, nodes[i]))
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continue;
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if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
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return -EINVAL;
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id = fdtdec_lookup(fdt, nodes[i]);
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switch (id) {
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case COMPAT_NVIDIA_TEGRA20_PCIE:
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soc = &tegra20_pcie_soc;
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break;
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return 0;
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}
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case COMPAT_NVIDIA_TEGRA30_PCIE:
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soc = &tegra30_pcie_soc;
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break;
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static int pci_tegra_probe(struct udevice *dev)
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{
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struct tegra_pcie *pcie = dev_get_priv(dev);
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int err;
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case COMPAT_NVIDIA_TEGRA124_PCIE:
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soc = &tegra124_pcie_soc;
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break;
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err = tegra_pcie_power_on(pcie);
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if (err < 0) {
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error("failed to power on");
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return err;
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}
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case COMPAT_NVIDIA_TEGRA210_PCIE:
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soc = &tegra210_pcie_soc;
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break;
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err = tegra_pcie_enable_controller(pcie);
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if (err < 0) {
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error("failed to enable controller");
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return err;
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}
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default:
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error("unsupported compatible: %s",
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fdtdec_get_compatible(id));
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continue;
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}
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err = tegra_pcie_setup_translations(dev);
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if (err < 0) {
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error("failed to decode ranges");
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return err;
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}
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pcie = malloc(sizeof(*pcie));
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if (!pcie) {
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error("failed to allocate controller");
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continue;
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}
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memset(pcie, 0, sizeof(*pcie));
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pcie->soc = soc;
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INIT_LIST_HEAD(&pcie->ports);
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err = tegra_pcie_parse_dt(fdt, nodes[i], pcie);
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if (err < 0) {
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free(pcie);
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continue;
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}
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err = tegra_pcie_power_on(pcie);
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if (err < 0) {
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error("failed to power on");
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continue;
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}
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err = tegra_pcie_enable_controller(pcie);
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if (err < 0) {
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error("failed to enable controller");
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continue;
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}
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tegra_pcie_setup_translations(pcie);
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err = tegra_pcie_enable(pcie);
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if (err < 0) {
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error("failed to enable PCIe");
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continue;
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}
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pcie->hose.first_busno = 0;
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pcie->hose.current_busno = 0;
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pcie->hose.last_busno = 0;
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pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
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NV_PA_SDRAM_BASE, pci_dram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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pci_set_region(&pcie->hose.regions[1], pcie->io.start,
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pcie->io.start, fdt_resource_size(&pcie->io),
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PCI_REGION_IO);
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pci_set_region(&pcie->hose.regions[2], pcie->mem.start,
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pcie->mem.start, fdt_resource_size(&pcie->mem),
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PCI_REGION_MEM);
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pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start,
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pcie->prefetch.start,
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fdt_resource_size(&pcie->prefetch),
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PCI_REGION_MEM | PCI_REGION_PREFETCH);
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pcie->hose.region_count = 4;
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pci_set_ops(&pcie->hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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tegra_pcie_read_conf,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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tegra_pcie_write_conf);
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pci_register_hose(&pcie->hose);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Enumerating devices...\n");
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printf("---------------------------------------\n");
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printf(" Device ID Description\n");
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printf(" ------ -- -----------\n");
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#endif
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pcie->hose.last_busno = pci_hose_scan(&pcie->hose);
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err = tegra_pcie_enable(pcie);
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if (err < 0) {
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error("failed to enable PCIe");
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return err;
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}
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return 0;
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}
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void pci_init_board(void)
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{
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const void *fdt = gd->fdt_blob;
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int count, nodes[1];
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static const struct dm_pci_ops pci_tegra_ops = {
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.read_config = pci_tegra_read_config,
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.write_config = pci_tegra_write_config,
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};
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tegra_pcie_board_init();
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static const struct udevice_id pci_tegra_ids[] = {
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{ .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
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{ .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
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{ .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
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{ .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
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{ }
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};
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count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
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COMPAT_NVIDIA_TEGRA210_PCIE,
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nodes, ARRAY_SIZE(nodes));
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if (process_nodes(fdt, nodes, count))
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return;
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count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
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COMPAT_NVIDIA_TEGRA124_PCIE,
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nodes, ARRAY_SIZE(nodes));
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if (process_nodes(fdt, nodes, count))
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return;
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count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
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COMPAT_NVIDIA_TEGRA30_PCIE,
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nodes, ARRAY_SIZE(nodes));
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if (process_nodes(fdt, nodes, count))
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return;
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count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
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COMPAT_NVIDIA_TEGRA20_PCIE,
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nodes, ARRAY_SIZE(nodes));
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if (process_nodes(fdt, nodes, count))
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return;
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}
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U_BOOT_DRIVER(pci_tegra) = {
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.name = "pci_tegra",
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.id = UCLASS_PCI,
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.of_match = pci_tegra_ids,
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.ops = &pci_tegra_ops,
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.ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
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.probe = pci_tegra_probe,
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.priv_auto_alloc_size = sizeof(struct tegra_pcie),
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};
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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