MIPS: mips32/cache.S: store cache line size in t8 register
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
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move RA, ra
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li t2, CONFIG_SYS_ICACHE_SIZE
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li t3, CONFIG_SYS_DCACHE_SIZE
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li t4, CONFIG_SYS_CACHELINE_SIZE
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li t8, CONFIG_SYS_CACHELINE_SIZE
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li v0, MIPS_MAX_CACHE_SIZE
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@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra)
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* Initialize the I-cache first,
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*/
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move a1, t2
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move a2, t4
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move a2, t8
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PTR_LA t7, mips_init_icache
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jalr t7
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@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
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* then initialize D-cache.
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*/
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move a1, t3
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move a2, t4
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move a2, t8
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PTR_LA t7, mips_init_dcache
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jalr t7
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