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MIPS: mips32/cache.S: store cache line size in t8 register

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Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
This commit is contained in:
Gabor Juhos 2013-06-13 12:59:35 +02:00 committed by Tom Rini
parent c325916563
commit ee8b1e2959
1 changed files with 3 additions and 3 deletions
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6
arch/mips/cpu/mips32/cache.S
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@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
li v0, MIPS_MAX_CACHE_SIZE
@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra)
* Initialize the I-cache first,
*/
move a1, t2
move a2, t4
move a2, t8
PTR_LA t7, mips_init_icache
jalr t7
@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
* then initialize D-cache.
*/
move a1, t3
move a2, t4
move a2, t8
PTR_LA t7, mips_init_dcache
jalr t7