ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>utp
Grzegorz Bernacki
Stefan Roese
parent
725671ccd2
commit
efa35cf12d
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@ -22,5 +22,13 @@
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#
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PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
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PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float
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PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float
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cfg=$(shell grep configs $(TOPDIR)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
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is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
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ifneq (,$(findstring CONFIG_440,$(is440)))
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PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
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else
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PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
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endif
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@ -294,11 +294,13 @@ skip_debug_init:
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mtspr ivor7,r1 /* Floating point unavailable */
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li r1,0x0c00
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mtspr ivor8,r1 /* System call */
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li r1,0x1000
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mtspr ivor10,r1 /* Decrementer (PIT for 440) */
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li r1,0x1400
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mtspr ivor13,r1 /* Data TLB error */
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li r1,0x0a00
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mtspr ivor9,r1 /* Auxiliary Processor unavailable */
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li r1,0x0900
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mtspr ivor10,r1 /* Decrementer */
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li r1,0x1300
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mtspr ivor13,r1 /* Data TLB error */
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li r1,0x1400
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mtspr ivor14,r1 /* Instr TLB error */
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li r1,0x2000
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mtspr ivor15,r1 /* Debug */
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@ -503,11 +505,81 @@ version_string:
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.ascii " (", __DATE__, " - ", __TIME__, ")"
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.ascii CONFIG_IDENT_STRING, "\0"
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/*
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* Maybe this should be moved somewhere else because the current
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* location (0x100) is where the CriticalInput Execption should be.
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*/
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. = EXC_OFF_SYS_RESET
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.globl _start_of_vectors
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_start_of_vectors:
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/* Critical input. */
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CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
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#ifdef CONFIG_440
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/* Machine check */
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MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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#else
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CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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#endif /* CONFIG_440 */
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + _START_OFFSET
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.long int_return - _start + _START_OFFSET
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + _START_OFFSET
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.long int_return - _start + _START_OFFSET
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#ifdef CONFIG_440
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
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STD_EXCEPTION(0xa00, APU, UnknownException)
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#endif
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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#ifdef CONFIG_440
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STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
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STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
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#else
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STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
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STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
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#endif
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CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
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.globl _end_of_vectors
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_end_of_vectors:
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. = _START_OFFSET
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#endif
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.globl _start
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_start:
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@ -1017,107 +1089,6 @@ start_ram:
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#ifndef CONFIG_NAND_SPL
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/*****************************************************************************/
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.globl _start_of_vectors
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_start_of_vectors:
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#if 0
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/*TODO Fixup _start above so we can do this*/
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/* Critical input. */
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CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
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#endif
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/* Machine check */
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CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_Alignment:
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.long AlignmentException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG
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addi r3,r1,STACK_FRAME_OVERHEAD
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li r20,MSR_KERNEL
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rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
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lwz r6,GOT(transfer_to_handler)
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mtlr r6
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blrl
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.L_ProgramCheck:
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.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
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.long int_return - _start + EXC_OFF_SYS_RESET
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/* No FPU on MPC8xx. This exception is not supposed to happen.
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*/
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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/* On the MPC8xx, this is a software emulation interrupt. It occurs
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* for all unimplemented and illegal instructions.
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*/
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STD_EXCEPTION(0x1000, PIT, PITException)
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STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
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STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
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STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
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STD_EXCEPTION(0x1500, Reserved5, UnknownException)
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STD_EXCEPTION(0x1600, Reserved6, UnknownException)
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STD_EXCEPTION(0x1700, Reserved7, UnknownException)
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STD_EXCEPTION(0x1800, Reserved8, UnknownException)
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STD_EXCEPTION(0x1900, Reserved9, UnknownException)
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STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
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STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
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STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
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STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
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STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
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STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
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CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x2100
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/*
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* This code finishes saving the registers to the exception frame
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* and jumps to the appropriate handler for the exception.
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@ -1133,28 +1104,12 @@ transfer_to_handler:
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SAVE_4GPRS(8, r21)
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SAVE_8GPRS(12, r21)
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SAVE_8GPRS(24, r21)
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#if 0
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andi. r23,r23,MSR_PR
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mfspr r23,SPRG3 /* if from user, fix up tss.regs */
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beq 2f
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addi r24,r1,STACK_FRAME_OVERHEAD
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stw r24,PT_REGS(r23)
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2: addi r2,r23,-TSS /* set r2 to current */
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tovirt(r2,r2,r23)
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#endif
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mflr r23
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andi. r24,r23,0x3f00 /* get vector offset */
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stw r24,TRAP(r21)
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li r22,0
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stw r22,RESULT(r21)
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mtspr SPRG2,r22 /* r1 is now kernel sp */
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#if 0
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addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
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cmplw 0,r1,r2
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cmplw 1,r1,r24
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crand 1,1,4
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bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
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#endif
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lwz r24,0(r23) /* virtual address of handler */
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lwz r23,4(r23) /* where to go when done */
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mtspr SRR0,r24
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@ -1215,16 +1170,64 @@ crit_return:
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr 990,r2 /* SRR2 */
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mtspr 991,r0 /* SRR3 */
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mtspr csrr0,r2
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mtspr csrr1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfci
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/* Cache functions.
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*/
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#ifdef CONFIG_440
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mck_return:
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mfmsr r28 /* Disable interrupts */
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li r4,0
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ori r4,r4,MSR_EE
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andc r28,r28,r4
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SYNC /* Some chip revs need this... */
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mtmsr r28
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SYNC
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lwz r2,_CTR(r1)
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lwz r0,_LINK(r1)
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mtctr r2
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mtlr r0
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lwz r2,_XER(r1)
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lwz r0,_CCR(r1)
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mtspr XER,r2
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mtcrf 0xFF,r0
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REST_10GPRS(3, r1)
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REST_10GPRS(13, r1)
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REST_8GPRS(23, r1)
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REST_GPR(31, r1)
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lwz r2,_NIP(r1) /* Restore environment */
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lwz r0,_MSR(r1)
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mtspr mcsrr0,r2
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mtspr mcsrr1,r0
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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lwz r1,GPR1(r1)
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SYNC
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rfmci
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#endif /* CONFIG_440 */
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/*
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* Cache functions.
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*
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* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
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* although for some cache-ralated calls stubs have to be provided to satisfy
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* symbols resolution.
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*
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*/
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#ifdef CONFIG_440
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.globl dcache_disable
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dcache_disable:
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blr
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.globl dcache_status
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dcache_status:
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blr
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#else
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flush_dcache:
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addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
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ori r9,r9,0x8000
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@ -1303,24 +1306,13 @@ dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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#endif
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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blr
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#if !defined(CONFIG_440)
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.globl wr_pit
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wr_pit:
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mtspr pit, r3
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blr
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#endif
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.globl wr_tcr
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wr_tcr:
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mtspr tcr, r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: out16 */
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/* Description: Output 16 bits */
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@ -1518,7 +1510,7 @@ relocate_code:
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* initialization, now running from RAM.
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*/
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addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
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addi r0, r10, in_ram - _start + _START_OFFSET
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mtlr r0
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blr /* NEVER RETURNS! */
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@ -1588,7 +1580,7 @@ clear_bss:
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*/
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.globl trap_init
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trap_init:
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lwz r7, GOT(_start)
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lwz r7, GOT(_start_of_vectors)
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lwz r8, GOT(_end_of_vectors)
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li r9, 0x100 /* reset vector always at 0x100 */
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@ -1608,35 +1600,48 @@ trap_init:
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/*
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* relocate `hdlr' and `int_return' entries
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*/
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li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
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li r8, Alignment - _start + EXC_OFF_SYS_RESET
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li r7, .L_MachineCheck - _start + _START_OFFSET
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li r8, Alignment - _start + _START_OFFSET
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2:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 2b
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li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
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li r7, .L_Alignment - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
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li r7, .L_ProgramCheck - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
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li r8, SystemCall - _start + EXC_OFF_SYS_RESET
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3:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 3b
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#ifdef CONFIG_440
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li r7, .L_FPUnavailable - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
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li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
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4:
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bl trap_reloc
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addi r7, r7, 0x100 /* next exception vector */
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cmplw 0, r7, r8
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blt 4b
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li r7, .L_Decrementer - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_APU - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_InstructionTLBError - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_DataTLBError - _start + _START_OFFSET
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bl trap_reloc
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#else /* CONFIG_440 */
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li r7, .L_PIT - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_DataTLBMiss - _start + _START_OFFSET
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bl trap_reloc
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#endif /* CONFIG_440 */
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li r7, .L_DebugBreakpoint - _start + _START_OFFSET
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bl trap_reloc
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#if !defined(CONFIG_440)
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addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
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@ -36,6 +36,8 @@
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#include <command.h>
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||||
#include <asm/processor.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
int (*debugger_exception_handler)(struct pt_regs *) = 0;
|
||||
#endif
|
||||
|
|
@ -45,8 +47,7 @@ extern unsigned long search_exception_table(unsigned long);
|
|||
|
||||
/* THIS NEEDS CHANGING to use the board info structure.
|
||||
*/
|
||||
#define END_OF_MEM 0x00400000
|
||||
|
||||
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
|
||||
|
||||
static __inline__ void set_tsr(unsigned long val)
|
||||
{
|
||||
|
|
@ -88,29 +89,29 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
|
|||
void
|
||||
print_backtrace(unsigned long *sp)
|
||||
{
|
||||
int cnt = 0;
|
||||
unsigned long i;
|
||||
int cnt = 0;
|
||||
unsigned long i;
|
||||
|
||||
printf("Call backtrace: ");
|
||||
while (sp) {
|
||||
if ((uint)sp > END_OF_MEM)
|
||||
break;
|
||||
printf("Call backtrace: ");
|
||||
while (sp) {
|
||||
if ((uint)sp > END_OF_MEM)
|
||||
break;
|
||||
|
||||
i = sp[1];
|
||||
if (cnt++ % 7 == 0)
|
||||
printf("\n");
|
||||
printf("%08lX ", i);
|
||||
if (cnt > 32) break;
|
||||
sp = (unsigned long *)*sp;
|
||||
}
|
||||
printf("\n");
|
||||
i = sp[1];
|
||||
if (cnt++ % 7 == 0)
|
||||
printf("\n");
|
||||
printf("%08lX ", i);
|
||||
if (cnt > 32) break;
|
||||
sp = (unsigned long *)*sp;
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
void show_regs(struct pt_regs * regs)
|
||||
{
|
||||
int i;
|
||||
|
||||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
|
||||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
|
||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
|
||||
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
|
||||
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
|
||||
|
|
@ -139,14 +140,14 @@ _exception(int signr, struct pt_regs *regs)
|
|||
{
|
||||
show_regs(regs);
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
|
||||
panic("Exception");
|
||||
}
|
||||
|
||||
void
|
||||
MachineCheckException(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long fixup;
|
||||
|
||||
unsigned long fixup, val;
|
||||
|
||||
/* Probing PCI using config cycles cause this exception
|
||||
* when a device is not present. Catch it and return to
|
||||
* the PCI exception handler.
|
||||
|
|
@ -161,26 +162,50 @@ MachineCheckException(struct pt_regs *regs)
|
|||
return;
|
||||
#endif
|
||||
|
||||
printf("Machine check in kernel mode.\n");
|
||||
printf("Machine Check Exception.\n");
|
||||
printf("Caused by (from msr): ");
|
||||
printf("regs %p ",regs);
|
||||
switch( regs->msr & 0x000F0000) {
|
||||
case (0x80000000>>12):
|
||||
printf("Machine check signal - probably due to mm fault\n"
|
||||
"with mmu off\n");
|
||||
break;
|
||||
case (0x80000000>>13):
|
||||
printf("Transfer error ack signal\n");
|
||||
break;
|
||||
case (0x80000000>>14):
|
||||
printf("Data parity signal\n");
|
||||
break;
|
||||
case (0x80000000>>15):
|
||||
printf("Address parity signal\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown values in msr\n");
|
||||
printf("regs %p ", regs);
|
||||
|
||||
val = get_esr();
|
||||
|
||||
#if !defined(CONFIG_440)
|
||||
if (val& ESR_IMCP) {
|
||||
printf("Instruction");
|
||||
mtspr(ESR, val & ~ESR_IMCP);
|
||||
} else
|
||||
printf("Data");
|
||||
printf(" machine check.\n");
|
||||
|
||||
#elif defined(CONFIG_440)
|
||||
if (val& ESR_IMCP){
|
||||
printf("Instruction Synchronous Machine Check exception\n");
|
||||
mtspr(SPRN_ESR, val & ~ESR_IMCP);
|
||||
}
|
||||
else {
|
||||
val = mfspr(MCSR);
|
||||
if (val & MCSR_IB)
|
||||
printf("Instruction Read PLB Error\n");
|
||||
if (val & MCSR_DRB)
|
||||
printf("Data Read PLB Error\n");
|
||||
if (val & MCSR_DWB)
|
||||
printf("Data Write PLB Error\n");
|
||||
if (val & MCSR_TLBP)
|
||||
printf("TLB Parity Error\n");
|
||||
if (val & MCSR_ICP){
|
||||
/*flush_instruction_cache(); */
|
||||
printf("I-Cache Parity Error\n");
|
||||
}
|
||||
if (val & MCSR_DCSP)
|
||||
printf("D-Cache Search Parity Error\n");
|
||||
if (val & MCSR_DCFP)
|
||||
printf("D-Cache Flush Parity Error\n");
|
||||
if (val & MCSR_IMPE)
|
||||
printf("Machine Check exception is imprecise\n");
|
||||
|
||||
/* Clear MCSR */
|
||||
mtspr(SPRN_MCSR, val);
|
||||
}
|
||||
#endif
|
||||
show_regs(regs);
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("machine check");
|
||||
|
|
@ -224,7 +249,7 @@ ProgramCheckException(struct pt_regs *regs)
|
|||
}
|
||||
|
||||
void
|
||||
PITException(struct pt_regs *regs)
|
||||
DecrementerPITException(struct pt_regs *regs)
|
||||
{
|
||||
/*
|
||||
* Reset PIT interrupt
|
||||
|
|
|
|||
|
|
@ -308,7 +308,7 @@
|
|||
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
|
||||
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
|
||||
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
|
||||
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
|
||||
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
|
||||
#ifdef CONFIG_BOOKE
|
||||
#define SPRN_SVR 0x3FF /* System Version Register */
|
||||
#else
|
||||
|
|
@ -451,6 +451,17 @@
|
|||
#define SPRN_PID1 0x279 /* Process ID Register 1 */
|
||||
#define SPRN_PID2 0x27a /* Process ID Register 2 */
|
||||
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
|
||||
#ifdef CONFIG_440
|
||||
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
|
||||
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
|
||||
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
|
||||
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
|
||||
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
|
||||
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
|
||||
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
|
||||
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
|
||||
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
|
||||
#endif
|
||||
#define ESR_ST 0x00800000 /* Store Operation */
|
||||
|
||||
#if defined(CONFIG_MPC86xx)
|
||||
|
|
@ -544,6 +555,8 @@
|
|||
#define SPRG7 SPRN_SPRG7
|
||||
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
|
||||
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
|
||||
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
|
||||
#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
|
||||
#define SVR SPRN_SVR /* System Version Register */
|
||||
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
|
||||
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CPCI440 1 /* Board is ebony */
|
||||
#define CONFIG_440GP 1 /* Specifc GP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
|
|
|
|||
|
|
@ -104,6 +104,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_METROBOX 1 /* Board is Metrobox */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ALPR 1 /* Board is ebony */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
|
||||
#define CONFIG_440EP 1 /* Specific PPC440EP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_EBONY 1 /* Board is ebony */
|
||||
#define CONFIG_440GP 1 /* Specifc GP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
//#define DEBUG
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_OCOTEA 1 /* Board is ebony */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_P3P440 1 /* Board is P3P440 */
|
||||
#define CONFIG_440GP 1 /* Specifc GP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
|
||||
#define CONFIG_440EP 1 /* Specific PPC440EP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#else
|
||||
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
|
||||
#endif
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
/* Detect Sequoia PLL input clock automatically via CPLD bit */
|
||||
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_TAISHAN 1 /* Board is taishan */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#define CONFIG_440GR 1 /* Specific PPC440GR support */
|
||||
#define CONFIG_HOSTNAME yellowstone
|
||||
#endif
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,15 @@
|
|||
/*--------------------------------------------------------------------- */
|
||||
#define srr2 0x3de /* save/restore register 2 */
|
||||
#define srr3 0x3df /* save/restore register 3 */
|
||||
|
||||
/*
|
||||
* 405 does not really have CSRR0/1 but SRR2/3 are used during critical
|
||||
* exception for the exact same purposes - let's alias them and have a
|
||||
* common handling in crit_return() and CRIT_EXCEPTION
|
||||
*/
|
||||
#define csrr0 srr2
|
||||
#define csrr1 srr3
|
||||
|
||||
#define dbsr 0x3f0 /* debug status register */
|
||||
#define dbcr0 0x3f2 /* debug control register 0 */
|
||||
#define dbcr1 0x3bd /* debug control register 1 */
|
||||
|
|
|
|||
|
|
@ -82,10 +82,7 @@
|
|||
#define ivor13 0x19d /* interrupt vector offset register 13 */
|
||||
#define ivor14 0x19e /* interrupt vector offset register 14 */
|
||||
#define ivor15 0x19f /* interrupt vector offset register 15 */
|
||||
#if defined(CONFIG_440GX) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||
#if defined(CONFIG_440)
|
||||
#define mcsrr0 0x23a /* machine check save/restore register 0 */
|
||||
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
|
||||
#define mcsr 0x23c /* machine check status register */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#ifndef __PPC4XX_H__
|
||||
#define __PPC4XX_H__
|
||||
|
||||
#define _START_OFFSET 0x2100
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
#include <ppc440.h>
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@
|
|||
* We assume sprg3 has the physical address of the current
|
||||
* task's thread_struct.
|
||||
*/
|
||||
#define EXCEPTION_PROLOG \
|
||||
#define EXCEPTION_PROLOG(reg1, reg2) \
|
||||
mtspr SPRG0,r20; \
|
||||
mtspr SPRG1,r21; \
|
||||
mfcr r20; \
|
||||
|
|
@ -235,8 +235,10 @@
|
|||
stw r22,_CTR(r21); \
|
||||
mfspr r20,XER; \
|
||||
stw r20,_XER(r21); \
|
||||
mfspr r22,SRR0; \
|
||||
mfspr r23,SRR1; \
|
||||
mfspr r20,DEAR; \
|
||||
stw r20,_DAR(r21); \
|
||||
mfspr r22,reg1; \
|
||||
mfspr r23,reg2; \
|
||||
stw r0,GPR0(r21); \
|
||||
stw r1,GPR1(r21); \
|
||||
stw r2,GPR2(r21); \
|
||||
|
|
@ -248,41 +250,6 @@
|
|||
* r21, r22 (SRR0), and r23 (SRR1).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Critical exception entry code. This is just like the other exception
|
||||
* code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
|
||||
*/
|
||||
#define CRITICAL_EXCEPTION_PROLOG \
|
||||
mtspr SPRG0,r20; \
|
||||
mtspr SPRG1,r21; \
|
||||
mfcr r20; \
|
||||
subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
|
||||
stw r20,_CCR(r21); /* save registers */ \
|
||||
stw r22,GPR22(r21); \
|
||||
stw r23,GPR23(r21); \
|
||||
mfspr r20,SPRG0; \
|
||||
stw r20,GPR20(r21); \
|
||||
mfspr r22,SPRG1; \
|
||||
stw r22,GPR21(r21); \
|
||||
mflr r20; \
|
||||
stw r20,_LINK(r21); \
|
||||
mfctr r22; \
|
||||
stw r22,_CTR(r21); \
|
||||
mfspr r20,XER; \
|
||||
stw r20,_XER(r21); \
|
||||
mfspr r22,990; /* SRR2 */ \
|
||||
mfspr r23,991; /* SRR3 */ \
|
||||
stw r0,GPR0(r21); \
|
||||
stw r1,GPR1(r21); \
|
||||
stw r2,GPR2(r21); \
|
||||
stw r1,0(r21); \
|
||||
mr r1,r21; /* set new kernel sp */ \
|
||||
SAVE_4GPRS(3, r21);
|
||||
/*
|
||||
* Note: code which follows this uses cr0.eq (set if from kernel),
|
||||
* r21, r22 (SRR2), and r23 (SRR3).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Exception vectors.
|
||||
*
|
||||
|
|
@ -293,30 +260,45 @@
|
|||
#define STD_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG; \
|
||||
EXCEPTION_PROLOG(SRR0, SRR1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,MSR_KERNEL; \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl ; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + EXC_OFF_SYS_RESET; \
|
||||
.long int_return - _start + EXC_OFF_SYS_RESET
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long int_return - _start + _START_OFFSET
|
||||
|
||||
#define CRIT_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG(csrr0, csrr1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long crit_return - _start + _START_OFFSET
|
||||
|
||||
#define CRIT_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
CRITICAL_EXCEPTION_PROLOG; \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl ; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + EXC_OFF_SYS_RESET; \
|
||||
.long crit_return - _start + EXC_OFF_SYS_RESET
|
||||
#ifdef CONFIG_440
|
||||
#define MCK_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long mck_return - _start + _START_OFFSET
|
||||
#endif /* CONFIG_440 */
|
||||
|
||||
#endif /* __PPC_ASM_TMPL__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue