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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

utp
Tom Rini 2016-01-03 10:32:24 -05:00
parent d83c25c318 ccf4326bac
commit f1993ca066
18 changed files with 268 additions and 22 deletions
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34
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -247,6 +247,39 @@ static void mxs_power_setup_5v_detect(void)
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
/**
* mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
* @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
*
* This function configures and then enables an alternative PLL clock source
* for the DC-DC converters.
*/
void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Select clocksource for DC-DC converters */
clrsetbits_le32(&power_regs->hw_power_misc,
POWER_MISC_FREQSEL_MASK,
freqsel);
setbits_le32(&power_regs->hw_power_misc,
POWER_MISC_SEL_PLLCLK);
}
/**
* mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
*
* Normally, there is no need to switch DC-DC clocksource. This is the reason,
* why this function is a stub and does nothing. However, boards can implement
* this function when required and call mxs_power_switch_dcdc_clocksource() to
* switch to an alternative clock source.
*/
__weak void mxs_power_setup_dcdc_clocksource(void)
{
debug("SPL: Using default DC-DC clocksource\n");
}
/**
* mxs_src_power_init() - Preconfigure the power block
*
@ -872,6 +905,7 @@ static void mxs_power_configure_power_source(void)
debug("SPL: Configuring power source\n");
mxs_power_setup_dcdc_clocksource();
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {

2
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -727,6 +727,8 @@ int enable_lcdif_clock(u32 base_addr)
reg = readl(&imx_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
return 0;
}
#endif

1
arch/arm/cpu/armv7/mx6/ddr.c
View File

@ -796,7 +796,6 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", ddr3_cfg->SRT);
debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
/*

8
arch/arm/imx-common/spl.c
View File

@ -20,7 +20,15 @@ u32 spl_boot_device(void)
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
unsigned int bmode = readl(&psrc->sbmr2);
/*
* Check for BMODE if serial downloader is enabled
* BOOT_MODE - see IMX6DQRM Table 8-1
*/
if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */
(gpr10_boot && (reg == 1)))
return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
/* EIM: See 8.5.1, Table 8-9 */

8
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -335,10 +335,10 @@
#include <asm/types.h>
/* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \
MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);

2
arch/arm/include/asm/arch-mxs/sys_proto.h
View File

@ -25,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
#endif
struct mxs_pair {

2
board/congatec/cgtqmx6eval/MAINTAINERS
View File

@ -3,4 +3,4 @@ M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
F: configs/cgtqmx6qeval_defconfig
F: configs/cgtqmx6eval_defconfig

2
board/congatec/cgtqmx6eval/cgtqmx6eval.c
View File

@ -404,7 +404,7 @@ static void setup_iomux_uart(void)
#ifdef CONFIG_MXC_SPI
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
SETUP_IOMUX_PADS(ecspi1_pads);
gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
}
#endif

87
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View File

@ -412,12 +412,42 @@ u32 get_board_rev(void)
}
#if defined(CONFIG_VIDEO_IPUV3)
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrbits_le32(&iomux->gpr[2],
IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
disable_lvds(dev);
imx_enable_hdmi_phy();
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = NULL,
.enable = NULL,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
@ -440,18 +470,69 @@ struct display_info_t const displays[] = {{
} } };
size_t display_count = ARRAY_SIZE(displays);
iomux_v3_cfg_t const backlight_pads[] = {
MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_backlight(void)
{
gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
setup_iomux_backlight();
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB_DI0 and LDB_DI1 clocks */
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
reg = readl(&mxc_ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@ -467,9 +548,6 @@ int overwrite_console(void)
int board_early_init_f(void)
{
setup_iomux_uart();
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
@ -494,6 +572,9 @@ int board_init(void)
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
setup_iomux_eimnor();
return 0;
}

10
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -150,11 +150,15 @@ static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int reg;
int reg, ret;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
ret = enable_fec_anatop_clock(0, ENET_125MHZ);
if (ret)
return ret;
imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads));
@ -163,14 +167,14 @@ static int setup_fec(void)
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
udelay(500);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(0, ENET_125MHZ);
return 0;
}
int board_eth_init(bd_t *bis)

51
doc/README.imx6
View File

@ -84,3 +84,54 @@ Address:
Reading bank 4:
Word 0x00000002: 9f027772 00000004
2. Using imx_usb_loader for first install with SPL
--------------------------------------------------
imx_usb_loader is a very nice tool by BoundaryDevice that
allow to install U-Boot without a JTAG debugger, using
the USB boot mode as described in the manual. It is
a replacement for Freescale's MFGTOOLS.
The sources can be found here:
https://github.com/boundarydevices/imx_usb_loader.git
Booting in USB mode, the i.MX6 announces itself to the Linux Host as:
Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc.
imx_usb_loader is able to download a single file (u-boot.imx)
to the board. For boards without SPL support, it is enough to
issue the command:
sudo ../imx_usb_loader/imx_usb -v u-boot.imx
Getting U-Boot when SPL support is active, it requires
two downloads. imx_usb_loader downloads the SPL into
OCRAM and starts it. SPL will check for a valid u-boot.img, and
because it is not found, it will wait for it using the y-modem
protocol via the console.
A first install is then possible by combining imx_usb_loader with
another tool such as kermit.
sudo ../imx_usb_loader/imx_usb -v SPL
kermit kermit_uboot
and kermit_uboot contains something like this (set line should be adjusted):
set line /dev/ttyUSB1
set speed 115200
SET CARRIER-WATCH OFF
set flow-control none
set handshake none
set prefixing all
set file type bin
set protocol ymodem
send u-boot.img
c
The last "c" command tells kermit (from ckermit package in most distros)
to switch from command line mode to communication mode, and when the
script is finished, the U-Boot prompt is shown in the same shell.

12
drivers/i2c/mxc_i2c.c
View File

@ -581,8 +581,16 @@ void bus_i2c_init(int index, int speed, int unused,
return;
}
mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
/*
* Warning: Be careful to allow the assignment to a static
* variable here. This function could be called while U-Boot is
* still running in flash memory. So such assignment is equal
* to write data to flash without erasing.
*/
if (idle_bus_fn)
mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
if (idle_bus_data)
mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
ret = enable_i2c_clk(1, index);
if (ret < 0) {

15
drivers/mmc/fsl_esdhc.c
View File

@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
#else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
#endif
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
clk = SYSCTL_PEREN | SYSCTL_CKEN;
#ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
#else
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
esdhc_setbits32(&regs->sysctl, clk);
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc)
esdhc_write32(&regs->scr, 0x00000040);
#endif
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
/* First reset the eSDHC controller */
esdhc_reset(regs);
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
#endif
writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));

20
drivers/net/fec_mxc.c
View File

@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*
* The i.MX28 and i.MX6 types have another field in the MSCR (aka
* MII_SPEED) register that defines the MDIO output hold time. Earlier
* versions are RAZ there, so just ignore the difference and write the
* register always.
* The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
* HOLDTIME + 1 is the number of clk cycles the fec is holding the
* output.
* The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
* Given that ceil(clkrate / 5000000) <= 64, the calculation for
* holdtime cannot result in a value greater than 3.
*/
register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
u32 pclk = imx_get_fecclk();
u32 speed = DIV_ROUND_UP(pclk, 5000000);
u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
#ifdef FEC_QUIRK_ENET_MAC
speed--;
#endif
speed <<= 1;
writel(speed, &eth->mii_speed);
writel(speed << 1 | hold << 8, &eth->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
}
@ -1097,6 +1109,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
mdio_unregister(bus);
free(bus);
return -ENOMEM;
}
@ -1108,6 +1121,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
mdio_unregister(bus);
free(bus);
}
return ret;

9
drivers/serial/serial_mxc.c
View File

@ -75,6 +75,7 @@
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
@ -135,6 +136,10 @@
DECLARE_GLOBAL_DATA_PTR;
#define TXTL 2 /* reset default */
#define RXTL 1 /* reset default */
#define RFDIV 4 /* divide input clock by 2 */
static void mxc_serial_setbrg(void)
{
u32 clk = imx_get_uartclk();
@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void)
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
| (TXTL << UFCR_TXTL_SHF)
| (RXTL << UFCR_RXTL_SHF);
__REG(UART_PHYS + UBIR) = 0xf;
__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);

2
include/configs/mx7_common.h
View File

@ -36,6 +36,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_FSL_CLK
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000

23
include/configs/novena.h
View File

@ -16,6 +16,7 @@
#define CONFIG_FIT
#define CONFIG_KEYBOARD
#include <config_distro_defaults.h>
#include "mx6_common.h"
/* U-Boot Commands */
@ -58,7 +59,7 @@
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs"
#define CONFIG_HOSTNAME novena
/* Physical Memory Map */
@ -190,6 +191,7 @@
#endif
/* Extra U-Boot environment. */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@ -199,6 +201,11 @@
"rootdev=/dev/mmcblk0p2\0" \
"netdev=eth0\0" \
"kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
"pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
"scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \
"ramdisk_addr_r=0x28000000\0" \
"fdt_addr_r=0x18000000\0" \
"fdtfile=imx6q-novena.dtb\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
@ -242,5 +249,19 @@
"fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
"fi ; " \
"fi\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(SATA, sata, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#else
#define CONFIG_EXTRA_ENV_SETTINGS
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */

2
include/fsl_esdhc.h
View File

@ -25,10 +25,12 @@
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000