B4860QDS: SGMII related updates
- Enable SGMII support for 0x8d Serdes 2 protocol.
- Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
- Updated debug statement
- Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
- Rename onboard PHY address defines for more readability
- Add these new Defines in B4860QDS.h file
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
utp
Shaveta Leekha
York Sun
parent
ffc1a87b91
commit
f1d8074c08
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@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
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* Lanes: A,B,C,D: PCI
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0xb1:
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case 0xb2:
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case 0x8c:
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case 0x8d:
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/*
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* Configuration:
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* SERDES: 2
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@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
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* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
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* 6 to on board SGMII phys
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*/
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fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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switch (serdes1_prtcl) {
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case 0x29:
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case 0x2a:
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/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
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debug("Setting phy addresses for FM1_DTSEC5: %x and"
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"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
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debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5,
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CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6,
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CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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break;
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#ifdef CONFIG_PPC_B4420
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case 0x17:
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case 0x18:
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/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
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debug("Setting phy addresses for FM1_DTSEC3: %x and"
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"FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
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debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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/* Fixing Serdes clock by programming FPGA register */
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QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4,
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CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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break;
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#endif
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default:
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@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
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switch (serdes2_prtcl) {
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case 0x17:
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case 0x18:
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debug("Setting phy addresses on SGMII Riser card for"
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"FM1_DTSEC ports: \n");
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debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2,
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@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
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break;
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case 0x48:
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case 0x49:
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debug("Setting phy addresses on SGMII Riser card for"
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"FM1_DTSEC ports: \n");
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debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2,
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@ -255,10 +258,12 @@ int board_eth_init(bd_t *bis)
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
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break;
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case 0x8d:
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case 0xb1:
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case 0xb2:
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debug("Setting phy addresses on SGMII Riser card for"
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"FM1_DTSEC ports: \n");
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case 0x8c:
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case 0x8d:
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debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4,
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@ -266,18 +271,18 @@ int board_eth_init(bd_t *bis)
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break;
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case 0x98:
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/* XAUI in Slot1 and Slot2 */
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debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
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debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
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CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC1,
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CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
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debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2,
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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break;
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case 0x9E:
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/* XAUI in Slot2 */
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debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
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debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2,
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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@ -329,17 +334,20 @@ int board_eth_init(bd_t *bis)
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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fm_info_set_mdio(i,
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miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
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miiphy_get_dev_by_name
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(DEFAULT_FM_TGEC_MDIO_NAME));
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break;
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case PHY_INTERFACE_MODE_NONE:
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fm_info_set_phy_address(i, 0);
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break;
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default:
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printf("Fman1: 10GSEC%u set to unknown interface %i\n",
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printf("Fman1: TGEC%u set to unknown interface %i\n",
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idx + 1, fm_info_get_enet_if(i));
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fm_info_set_phy_address(i, 0);
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break;
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}
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}
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cpu_eth_init(bis);
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#endif
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@ -357,15 +365,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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sprintf(alias, "phy_sgmii_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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fdt_status_okay_by_alias(fdt, alias);
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}
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}
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/*
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* Set status to disabled for unused ethernet node
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*/
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void fdt_fixup_board_enet(void *fdt)
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{
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int i;
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char alias[32];
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_NONE:
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sprintf(alias, "ethernet%u", i);
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@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_FMAN_ENET
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#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
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#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
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#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
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#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
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/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
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#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
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